Arrow Electronics
Senior ASIC Design Engineer (eInfochips Inc)
Arrow Electronics, San Jose, California, United States, 95199
Position
Senior ASIC Design Engineer (eInfochips Inc) What candidate will Be Doing
Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC. What We Are Looking For
A bachelor’s degree in electrical or computer engineering with a minimum of 10 years of experience in ASIC or a related field, or a Master’s Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs. Proficiency in synthesis, place, and route flows for FPGAs. In-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC). Demonstrated experience in RTL coding using Verilog/SystemVerilog and integration of third-party IPs. Metho dical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development. Preferred Qualifications
Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms. Strong understanding of PCIe, DDR, Ethernet, and Networking Protocols. Proficiency in prototyping ARM or RISCV CPUs. Exceptional scripting skills using TCL, Python, or Perl. What’s In It For You
Competitive financial compensation with various plans and a solid benefits package. Medical, Dental, Vision Insurance 401k with Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA) / Health Reimbursement Account (HRA) Options Paid Time Off (sick, holiday, vacation, etc.) Tuition Reimbursement Growth Opportunities And more Education
Bachelor's Degree Work Arrangement
Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership. Location
On-Site in San Jose, CA About EInfochips
eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. The organization collaborates with top technology partners and operates within Arrow’s global footprint to accelerate connected products and edge-to-cloud capabilities. EEO Statement
Arrow is an equal opportunity employer. All applicants will be considered for employment without regard to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) Annual Hiring Range / Hourly Rate
$92,200.00 - $214,500.00 Actual compensation offer may vary based on geographic location, experience, education, and/or skill level. Pay ratio between base pay and target incentive (if applicable) will be finalized at offer. Additional Details
Time Type: Full time Job Category: Engineering Services Seniority level: Mid-Senior level Employment type: Full-time Industries: Technology, Information and Internet
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Senior ASIC Design Engineer (eInfochips Inc) What candidate will Be Doing
Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC. What We Are Looking For
A bachelor’s degree in electrical or computer engineering with a minimum of 10 years of experience in ASIC or a related field, or a Master’s Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs. Proficiency in synthesis, place, and route flows for FPGAs. In-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC). Demonstrated experience in RTL coding using Verilog/SystemVerilog and integration of third-party IPs. Metho dical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development. Preferred Qualifications
Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms. Strong understanding of PCIe, DDR, Ethernet, and Networking Protocols. Proficiency in prototyping ARM or RISCV CPUs. Exceptional scripting skills using TCL, Python, or Perl. What’s In It For You
Competitive financial compensation with various plans and a solid benefits package. Medical, Dental, Vision Insurance 401k with Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA) / Health Reimbursement Account (HRA) Options Paid Time Off (sick, holiday, vacation, etc.) Tuition Reimbursement Growth Opportunities And more Education
Bachelor's Degree Work Arrangement
Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership. Location
On-Site in San Jose, CA About EInfochips
eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. The organization collaborates with top technology partners and operates within Arrow’s global footprint to accelerate connected products and edge-to-cloud capabilities. EEO Statement
Arrow is an equal opportunity employer. All applicants will be considered for employment without regard to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) Annual Hiring Range / Hourly Rate
$92,200.00 - $214,500.00 Actual compensation offer may vary based on geographic location, experience, education, and/or skill level. Pay ratio between base pay and target incentive (if applicable) will be finalized at offer. Additional Details
Time Type: Full time Job Category: Engineering Services Seniority level: Mid-Senior level Employment type: Full-time Industries: Technology, Information and Internet
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