Silicon Photonics Packaging Engineer - San Francisco, CA 94110 (Hybrid) at Women

Overview

Silicon Photonics Packaging Engineer - San Francisco, CA 94110 (Hybrid) job at Women Impact Tech. San Francisco, CA.

We are seeking a Silicon Photonics Packaging Engineer to join our cutting-edge hardware engineering team. In this role, you will design and develop microelectronic assembly processes for automotive-grade receiver and transmitter modules , enabling the next generation of high-performance LiDAR and photonic systems.

This is a unique opportunity to work on complex IC packaging, system integration, and process development , collaborating with world-class teams and external manufacturing partners to bring innovative products into mass production.

Responsibilities

• Design and optimize microelectronic assembly processes from wafer fab to package integration
• Define specifications for custom IC package designs and chip carriers , working with external partners to deliver production-ready solutions
• Execute process optimization, design validation, failure analysis, and sample builds for package development and automotive qualification
• Lead yield analysis and drive improvements/corrective actions for silicon process and assembly reliability
• Collaborate with global vendors to develop new packaging processes, prototypes, and tooling
• Manage vendor sourcing, vetting, quoting, and low-volume procurement for diverse components (substrates, epoxies, coated glass, PCBAs, tooling)
• Drive mass production readiness , collaborating across engineering and operations teams

Basic Qualifications

• 5+ years in Semiconductor Package/Process Development , or 2+ years with a Master’s degree
• Experience with multi-layer ceramic, CMOS image sensor, BGA packages, and organic substrates
• Hands-on experience with wafer-level processing (thin-film deposition, RIE silicon processing, wafer bonding, spin coat/lift-off, wafer dice/test)
• Proficiency in automated microelectronic and photonic assembly (wafer inspection, die attach, wire bonding, vision inspection, underfill/encapsulation)
• Working knowledge of Failure Analysis tools (X-ray, 3D interferometry, SEM, cross-sectioning, destructive testing, etc.)
• Strong understanding of semiconductor packaging for high-reliability environments

Bonus Qualifications

• Bachelor’s or Master’s in Electrical or Mechanical Engineering
• Experience with optical systems or CMOS image sensor architecture
• Exposure to ATE package test environments
• Familiarity with statistical analysis methods for production processes
• Automotive qualification experience (AEC-Q100 or similar)

Note: Candidate must be within 15 minutes commute to 94110 zip code or open to relocate to the city.

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