Logo
Mirafra Technologies

RTL Design Engineer

Mirafra Technologies, San Jose, California, United States, 95199

Save Job

Responsibilities

Strong Logic Design, RTL coding (Verilog HDL) and debugging skills Analyze and resolve Lint, CDC and RDC issues in the design Understanding of low power design and validation techniques including UPF Experience with constraint generation, timing closure analysis, formal verification, low power checks using UPF flows and ECO implementation. Experience with writing assertions and doing negative checks to validate assertions Experience with Silicon validation/Bring-up Experience with the following are highly desired ARM CPUs Memory controllers Peripherals such as I2C, SPI, UART, LVDS, QSPI and SPMI Peripherals and interconnect protocols such as APB, AHB and AXI Experience with the following are a definite advantage Scripting languages such as (Python perl/tcl) Convert DV test cases to Python scripts to check Silicon functionality Other Requirements Self-motivated Ability to work independently Good verbal and written communication skills Ability to work with remote and cross functional teams Seniority level

Mid-Senior level Employment type

Full-time Job function

Engineering, Design, and Information Technology Industries

Software Development, Computer Hardware Manufacturing, and Semiconductor Manufacturing We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

#J-18808-Ljbffr