Acceler8 Talent
Base pay range
$275,000.00/yr - $300,000.00/yr In this role, you will work with Acceler8 Talent on a breakthrough computing initiative focused on real-time computing over encrypted datasets, enabling secure, high-performance processing in edge and cloud environments. Their proprietary architecture is designed for compute-heavy applications like Fully Homomorphic Encryption (FHE). Overview
They’re looking for an experienced
DFT Architect
to lead the design-for-test strategy across complex SoC/ASIC programs. This is a hands-on leadership role for someone who can balance technical execution with team direction and cross-functional coordination. In this role, you will
Define and own DFT architecture and methodology for advanced SoCs Lead scan insertion, MBIST, LBIST, JTAG, boundary scan, and ATPG implementations Manage and mentor a team of DFT engineers through all phases of development Collaborate with RTL, PD, and verification teams for smooth DFT integration and signoff Support post-silicon bring-up, test development, and yield improvement efforts You should bring
10+ years of DFT experience, including 3+ years in technical leadership or management Deep knowledge of DFT tools and flows (Tessent, DFTMAX, Modus, etc.) Hands-on experience with scan, BIST, and boundary scan techniques Strong understanding of RTL-to-GDSII flows, timing closure, and test coverage optimization Familiarity with scripting (Python, Perl, TCL) to automate and enhance test processes Bonus if you have
Background in safety-critical or mission-critical applications (automotive, aerospace, etc.) Experience with low-power DFT techniques and production ATE test optimization Seniority level
Mid-Senior level Employment type
Full-time Job function
Industries Computer Hardware Manufacturing and Semiconductor Manufacturing
#J-18808-Ljbffr
$275,000.00/yr - $300,000.00/yr In this role, you will work with Acceler8 Talent on a breakthrough computing initiative focused on real-time computing over encrypted datasets, enabling secure, high-performance processing in edge and cloud environments. Their proprietary architecture is designed for compute-heavy applications like Fully Homomorphic Encryption (FHE). Overview
They’re looking for an experienced
DFT Architect
to lead the design-for-test strategy across complex SoC/ASIC programs. This is a hands-on leadership role for someone who can balance technical execution with team direction and cross-functional coordination. In this role, you will
Define and own DFT architecture and methodology for advanced SoCs Lead scan insertion, MBIST, LBIST, JTAG, boundary scan, and ATPG implementations Manage and mentor a team of DFT engineers through all phases of development Collaborate with RTL, PD, and verification teams for smooth DFT integration and signoff Support post-silicon bring-up, test development, and yield improvement efforts You should bring
10+ years of DFT experience, including 3+ years in technical leadership or management Deep knowledge of DFT tools and flows (Tessent, DFTMAX, Modus, etc.) Hands-on experience with scan, BIST, and boundary scan techniques Strong understanding of RTL-to-GDSII flows, timing closure, and test coverage optimization Familiarity with scripting (Python, Perl, TCL) to automate and enhance test processes Bonus if you have
Background in safety-critical or mission-critical applications (automotive, aerospace, etc.) Experience with low-power DFT techniques and production ATE test optimization Seniority level
Mid-Senior level Employment type
Full-time Job function
Industries Computer Hardware Manufacturing and Semiconductor Manufacturing
#J-18808-Ljbffr