Renesas
Key Responsibilities
Execute subsystem/block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.
Collaborate closely with SoC-level teams to align on clocking and floorplanning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.
Collaborate cross-functionally with physical design, microarchitecture, and verification teams to resolve timing bottlenecks and optimize design margins.
Mentor and guide physical design engineers within the subsystem teams, promoting best practices and methodology adoption.
Work cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure.
Proactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions.
Qualifications
10+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below). Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level. Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them. Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms. Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development. Deep knowledge of SoC design flows with proven ability to work closely with timing closure, power integrity, clocking, verification. Solid understanding of low-power design techniques and power-aware physical implementation.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity and Inclusion Statement. #J-18808-Ljbffr
Qualifications
10+ years of experience in physical design focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below). Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level. Solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating; candidate is expected to collaborate effectively on SoC-level activities but not lead them. Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms. Proficient in scripting and automation (Tcl, Python, Perl) to support closure flows and methodology development. Deep knowledge of SoC design flows with proven ability to work closely with timing closure, power integrity, clocking, verification. Solid understanding of low-power design techniques and power-aware physical implementation.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity and Inclusion Statement. #J-18808-Ljbffr