Jobot
Overview
Senior Digital Design Engineer role in Seattle, WA. You will play a key role in developing the system architecture and RTL codebase for the FPGA module that performs localization and decodes packets from ground-based BLE device transmissions. You’ll collaborate closely with a cross-functional team of system, hardware, and software engineers to optimize the throughput, accuracy, power efficiency, and reliability of the Hubble satellite constellation. This is a full-time position based in Seattle, WA. Responsibilities
Develop system architecture and RTL codebase for FPGA module focused on localization and packet decoding of BLE transmissions. Collaborate with cross-functional teams (system, hardware, software) to optimize throughput, accuracy, power efficiency, and reliability. Lead projects from concept to reality with urgency and a results-oriented approach. Describe and iterate requirements, support design reviews, and ensure end-to-end validation with RF and software teams. Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in FPGA-based digital design with emphasis on real-time signal processing and communication systems. Proven expertise in RTL design (Verilog/SystemVerilog) for high-throughput, low-latency digital receivers. Experience with high-speed memory interfaces (DDR/DDR3/DDR4) including controller integration, timing constraints, and performance tuning. Proficient in integrating and validating high-speed serial interfaces (LVDS, SPI, I2C, UART, SERDES-based links). FPGA synthesis, timing closure, and resource optimization (Xilinx or Intel/Altera). Experience with simulation/verification tools (ModelSim, Questa, Vivado, VUnit) and scripting (Python, Tcl). Strong DSP knowledge (filters, correlation, decimation, fixed-point arithmetic). Experience developing packet decoders for wireless protocols (BLE, ZigBee, LoRa, or custom PHYs). Ability to work with RF engineers, firmware developers, and systems engineers for end-to-end validation. Strong interpersonal and written/verbal communication skills; ability to work independently and in fast-paced environments. Desirable
Experience designing distributed DSP systems across multiple FPGAs or compute nodes. Familiarity with ARM cores, peripheral interfacing (SPI, I2C, AXI), and embedded Linux (Petalinux). Knowledge of synchronization techniques (preamble detection, timing recovery, frequency offset correction). Experience with lab tools (oscilloscopes, logic analyzers, RF test equipment). Knowledge of low-power design for space-based or resource-constrained systems; BLE physical layer familiarity. Compensation & Benefits
Salary range: $180,000 per year (base). Comprehensive benefits – Health, Dental, Vision, HSA options. Unlimited PTO; Parental Leave; Commuter Benefits; Learning & Development Allowance. Health & Wellness Stipend; Sabbatical Program; access to cutting-edge space tech; team retreats and more. Company & Equal Opportunity
Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds. Want to learn more about this role and Jobot? Click our Jobot logo and follow our LinkedIn page!
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Senior Digital Design Engineer role in Seattle, WA. You will play a key role in developing the system architecture and RTL codebase for the FPGA module that performs localization and decodes packets from ground-based BLE device transmissions. You’ll collaborate closely with a cross-functional team of system, hardware, and software engineers to optimize the throughput, accuracy, power efficiency, and reliability of the Hubble satellite constellation. This is a full-time position based in Seattle, WA. Responsibilities
Develop system architecture and RTL codebase for FPGA module focused on localization and packet decoding of BLE transmissions. Collaborate with cross-functional teams (system, hardware, software) to optimize throughput, accuracy, power efficiency, and reliability. Lead projects from concept to reality with urgency and a results-oriented approach. Describe and iterate requirements, support design reviews, and ensure end-to-end validation with RF and software teams. Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in FPGA-based digital design with emphasis on real-time signal processing and communication systems. Proven expertise in RTL design (Verilog/SystemVerilog) for high-throughput, low-latency digital receivers. Experience with high-speed memory interfaces (DDR/DDR3/DDR4) including controller integration, timing constraints, and performance tuning. Proficient in integrating and validating high-speed serial interfaces (LVDS, SPI, I2C, UART, SERDES-based links). FPGA synthesis, timing closure, and resource optimization (Xilinx or Intel/Altera). Experience with simulation/verification tools (ModelSim, Questa, Vivado, VUnit) and scripting (Python, Tcl). Strong DSP knowledge (filters, correlation, decimation, fixed-point arithmetic). Experience developing packet decoders for wireless protocols (BLE, ZigBee, LoRa, or custom PHYs). Ability to work with RF engineers, firmware developers, and systems engineers for end-to-end validation. Strong interpersonal and written/verbal communication skills; ability to work independently and in fast-paced environments. Desirable
Experience designing distributed DSP systems across multiple FPGAs or compute nodes. Familiarity with ARM cores, peripheral interfacing (SPI, I2C, AXI), and embedded Linux (Petalinux). Knowledge of synchronization techniques (preamble detection, timing recovery, frequency offset correction). Experience with lab tools (oscilloscopes, logic analyzers, RF test equipment). Knowledge of low-power design for space-based or resource-constrained systems; BLE physical layer familiarity. Compensation & Benefits
Salary range: $180,000 per year (base). Comprehensive benefits – Health, Dental, Vision, HSA options. Unlimited PTO; Parental Leave; Commuter Benefits; Learning & Development Allowance. Health & Wellness Stipend; Sabbatical Program; access to cutting-edge space tech; team retreats and more. Company & Equal Opportunity
Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds. Want to learn more about this role and Jobot? Click our Jobot logo and follow our LinkedIn page!
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