OVT group
Overview
Work on detailed transistor level design of analog and mixed signal circuits in memory (DRAM/SRAM) for display chip or image sensor. Perform the whole chip simulation along with the block level, transistor level schematic simulation with Cadence OrCAD, Altium Designer, and SPICE. Perform the block level and transistor level layout and circuit design. Collaborate with verification, process, test, and application engineers to debug, characterize and optimize the performance. Responsibilities
Design and simulate analog and mixed-signal circuits at transistor and block levels for memory (DRAM/SRAM) applications in display chips or image sensors. Perform chip-level, block-level, and transistor-level schematic simulations using Cadence OrCAD, Altium Designer, and SPICE. Execute block-level and transistor-level layout and circuit design. Collaborate with verification, process, test, and application engineers to debug, characterize, and optimize performance. Qualifications
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or related fields. Require six months of experience in power electronics circuits. Experience shall include: Switching regulators, power circuit design, and efficiency optimization for high-performance computing applications. Experience in Cadence OrCAD, Altium Designer, and SPICE-based simulation tools. Experience in analyzing PCB power issues, optimizing motherboard layouts, and troubleshooting manufacturing process challenges. Experience in power measurement and optimization, transient analysis, power profiling. Compensation
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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Work on detailed transistor level design of analog and mixed signal circuits in memory (DRAM/SRAM) for display chip or image sensor. Perform the whole chip simulation along with the block level, transistor level schematic simulation with Cadence OrCAD, Altium Designer, and SPICE. Perform the block level and transistor level layout and circuit design. Collaborate with verification, process, test, and application engineers to debug, characterize and optimize the performance. Responsibilities
Design and simulate analog and mixed-signal circuits at transistor and block levels for memory (DRAM/SRAM) applications in display chips or image sensors. Perform chip-level, block-level, and transistor-level schematic simulations using Cadence OrCAD, Altium Designer, and SPICE. Execute block-level and transistor-level layout and circuit design. Collaborate with verification, process, test, and application engineers to debug, characterize, and optimize performance. Qualifications
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or related fields. Require six months of experience in power electronics circuits. Experience shall include: Switching regulators, power circuit design, and efficiency optimization for high-performance computing applications. Experience in Cadence OrCAD, Altium Designer, and SPICE-based simulation tools. Experience in analyzing PCB power issues, optimizing motherboard layouts, and troubleshooting manufacturing process challenges. Experience in power measurement and optimization, transient analysis, power profiling. Compensation
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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