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Senior SoC RTL Design Engineer

Jobs via Dice, Santa Clara

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Overview

Senior SoC RTL Design Engineer to lead the SoC chip-top RTL design and integration, ensuring seamless integration of subsystems, IPs, and hard macros into a complete SoC design. Responsibilities include RTL implementation, synthesis constraints, I/O padring design, power/thermal analysis, and collaboration with physical design to drive timing closure and system-level optimizations. This role requires deep expertise in SoC architecture, RTL design, synthesis, timing, and physical implementation, with cross-discipline experience across DFT, Physical Design (PD), Power/IR Drop analysis, and Package Integration. The engineer will collaborate with the Senior DFT Engineer to ensure seamless DFT integration at the SoC level.

Responsibilities

  • Own the chip-top RTL design and integration, ensuring seamless functionality across subsystems.
  • Integrate internal and external IPs, including CPU cores, analog IP, memories, and peripherals.
  • Work closely with subsystem RTL teams to ensure smooth SoC-level integration.
  • Develop and maintain a modular, scalable, and synthesizable RTL codebase.
  • Design and implement the SoC s input-output (I/O) ring (padring) and ensure proper integration of hard macros (PLLs, PMUs, SRAMs, PHYs).
  • Define ESD protection and power domain partitioning strategies at the SoC level.
  • Define and validate timing constraints (SDC) and synthesis constraints for the SoC.
  • Collaborate with the Physical Design (PD) team on floorplanning, placement, and routing, driving timing closure and robust CDCs and reset strategies.
  • Collaborate with PDN experts to optimize power distribution networks and minimize IR drop, while meeting thermal design power constraints and package limits.
  • Work with package engineers on package design, parasitic noise, crosstalk, and EMI considerations.
  • Collaborate with the Senior DFT Engineer to integrate scan chains, BIST controllers, and JTAG at the SoC level, ensuring DFT readiness including boundary scan, scan compression, and ATPG pattern validation.
  • Support post-silicon validation and debugging in collaboration with test engineering teams.

Qualifications

  • 8+ years of experience in SoC RTL design, integration, and implementation.
  • Strong expertise in SystemVerilog and HDL-based RTL design for complex SoCs.
  • Experience in chip-level integration, including IPs, hard macros, and analog/digital interfaces.
  • Solid knowledge of clocking architectures, CDC, and reset domain crossings (RDC).
  • Hands-on experience with timing constraints (SDC), STA, and timing closure.
  • Experience with EDA tools: Synthesis (e.g., Synopsys Design Compiler, Cadence Genus) and Timing Analysis (e.g., PrimeTime, Tempus).
  • Physical implementation collaboration including floorplanning and power/thermal analysis.
  • Understanding of PDN design, IR drop, power integrity, and package constraints.
  • Familiarity with DFT methodologies, including scan, BIST, and ATPG integration.
  • Strong problem-solving skills and ability to work in a cross-functional engineering team.
  • Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or a related field.

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