NVIDIA
Senior Design Engineer, Coherent High Speed Interconnect
NVIDIA, Santa Clara, California, us, 95053
Overview NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team.
The following information provides an overview of the skills, qualities, and qualifications needed for this role. NVIDIA has pioneered visual computing and continues to lead in the AI computing era with GPU-based deep learning. This role focuses on architecture and design of state-of-the-art high speed coherent interconnects to enable chiplet-based products and coherent interconnection across GPUs, DPUs, and CPUs. What You'll Be Doing
You will be working on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs. Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect. The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ This position offers the opportunity to have real impact in a dynamic, technology-focused company affecting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What We Need to See
BS or equivalent experience in Electrical Engineering or Computer Engineering or related degree required; advanced degrees (MS, PhD) are a plus. 5+ years of relevant design experience. Knowledge of industry standard interconnect protocols like PCIe, CXL, AXI, CHI is useful. Understanding or experience with link layer stacks including Data link layer and Physical layer. Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc.), PCIe, SerDes. Experience and knowledge in architecture, RTL design, performance analysis and power optimization. Strong working knowledge of Verilog or SystemVerilog. Good communication and interpersonal skills. A history of mentoring junior engineers and interns is a plus. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 6, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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The following information provides an overview of the skills, qualities, and qualifications needed for this role. NVIDIA has pioneered visual computing and continues to lead in the AI computing era with GPU-based deep learning. This role focuses on architecture and design of state-of-the-art high speed coherent interconnects to enable chiplet-based products and coherent interconnection across GPUs, DPUs, and CPUs. What You'll Be Doing
You will be working on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs. Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect. The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. To learn more about NVIDIA's ultra-fast chip interconnect technology visit: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ This position offers the opportunity to have real impact in a dynamic, technology-focused company affecting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What We Need to See
BS or equivalent experience in Electrical Engineering or Computer Engineering or related degree required; advanced degrees (MS, PhD) are a plus. 5+ years of relevant design experience. Knowledge of industry standard interconnect protocols like PCIe, CXL, AXI, CHI is useful. Understanding or experience with link layer stacks including Data link layer and Physical layer. Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc.), PCIe, SerDes. Experience and knowledge in architecture, RTL design, performance analysis and power optimization. Strong working knowledge of Verilog or SystemVerilog. Good communication and interpersonal skills. A history of mentoring junior engineers and interns is a plus. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 6, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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