Qualcomm
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ASICS Design Verification Engineer
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Qualcomm Company
Below covers everything you need to know about what this opportunity entails, as well as what is expected from applicants. Qualcomm Technologies, Inc. Job Area Engineering Group > ASICS Engineering Overview As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The position involves comprehensive pre-silicon test planning for digital power IPs, testbench development using verification methodologies such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency. Responsibilities
Contribute to the complete verification lifecycle from concept to tape-out and post-silicon support. Perform comprehensive pre-silicon test planning for digital power IPs. Develop testbenches using advanced verification methodologies such as SystemVerilog-UVM. Develop coverage plans and assertion models; engage in formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Develop automation to improve verification efficiency. QualificationsMinimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications
Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field. 6+ years of experience with ASIC design and verification tools, techniques, and methodology. 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL. 6+ years of experience with computer architecture fundamentals, object-oriented programming concepts and C or C++ programming skills. 6+ years of experience with developing block-level testbench environments using SystemVerilog. 6+ years of experience with verification methodologies through coursework or past experiences (UVM or OVM) and exposure to assertion-based formal verification. 6+ years of experience with scripting/automation using Perl or Python. Experience with AMBA Bus protocol (AXI/AHB/APB) is desirable. Knowledge or experience with Assertion Based Formal Verification is desirable. Employment Details
Seniority level: Not Applicable Employment type: Full-time Job function: Other Industries: Telecommunications EEO: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay Range And Other Compensation & Benefits:
$140,000.00 - $210,000.00 The pay range reflects minimum to maximum for the location. Salary is one component of total compensation, with a competitive annual discretionary bonus program and potential RSU grants. Our benefits package supports work, home, and personal life. Your recruiter can share more details. For more information about this role, please contact Qualcomm Careers. Referrals increase your chances of interviewing at Qualcomm by 2x. Get notified about new Design Verification Engineer jobs in
San Diego, CA .
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ASICS Design Verification Engineer
role at
Qualcomm Company
Below covers everything you need to know about what this opportunity entails, as well as what is expected from applicants. Qualcomm Technologies, Inc. Job Area Engineering Group > ASICS Engineering Overview As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The position involves comprehensive pre-silicon test planning for digital power IPs, testbench development using verification methodologies such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency. Responsibilities
Contribute to the complete verification lifecycle from concept to tape-out and post-silicon support. Perform comprehensive pre-silicon test planning for digital power IPs. Develop testbenches using advanced verification methodologies such as SystemVerilog-UVM. Develop coverage plans and assertion models; engage in formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Develop automation to improve verification efficiency. QualificationsMinimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Preferred Qualifications
Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field. 6+ years of experience with ASIC design and verification tools, techniques, and methodology. 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL. 6+ years of experience with computer architecture fundamentals, object-oriented programming concepts and C or C++ programming skills. 6+ years of experience with developing block-level testbench environments using SystemVerilog. 6+ years of experience with verification methodologies through coursework or past experiences (UVM or OVM) and exposure to assertion-based formal verification. 6+ years of experience with scripting/automation using Perl or Python. Experience with AMBA Bus protocol (AXI/AHB/APB) is desirable. Knowledge or experience with Assertion Based Formal Verification is desirable. Employment Details
Seniority level: Not Applicable Employment type: Full-time Job function: Other Industries: Telecommunications EEO: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay Range And Other Compensation & Benefits:
$140,000.00 - $210,000.00 The pay range reflects minimum to maximum for the location. Salary is one component of total compensation, with a competitive annual discretionary bonus program and potential RSU grants. Our benefits package supports work, home, and personal life. Your recruiter can share more details. For more information about this role, please contact Qualcomm Careers. Referrals increase your chances of interviewing at Qualcomm by 2x. Get notified about new Design Verification Engineer jobs in
San Diego, CA .
#J-18808-Ljbffr