Chelsea Search Group
Senior Power Management Engineer
Chelsea Search Group, San Jose, California, United States, 95199
Senior Power Management Engineer
US Citizen or US Permanent Resident
San Jose, California or remote from any US location
Responsibilities •Conduct power modeling & analysis: use UPF driven flows for early RTL power budgeting, leakage/dynamic power estimation, DVFS schemes, gate level impact, and thermal aware power sequencing. •Coordinate cross team: align power intent integration, sequencing handshakes, API behavior, and cross domain safety with firmware, verification, RTL, physical design, and PMIC teams. •Define UPF/CPF power intent architecture: establish power domains, power states, retention policies, isolation strategies, and level shifter insertion across the SoC hierarchy. •Develop and implement advanced power management architecture-including Dynamic Voltage and Frequency Scaling (DVFS), power gating, and low power states-to enhance energy efficiency across SoC domains and use case •Micro-architect, Design and Develop power management unit for Next Gen AI accelerator chip •Partner with firmware teams: leverage knowledge of C/C++ to review and reason about firmware-controlled PMIC interactions, power state transitions, retention restore logic, and isolation control-without performing firmware development directly. •Specify structural low power elements: design isolation cells, level shifters, power switches, and retention (save/restore) flows to ensure correct behavior across power states. •Support low power verification: establish UPF aware testbench strategies, static and dynamic low power checks for EDA signoff, ensuring correct insertion of retention and isolation logic and domain handshakes. •Support silicon bring up: assist with post silicon validation of retention sequences, isolation logic, voltage transitions, and state handovers during lab bring up.
Requirements: •5+ years of experience in SoC low power architecture and flows, especially UPF/CPF intent specification •Bachelor's or Master's in EE, CE, or related technical field. •Experience with scripting (e.g., Python, Tcl, Perl) to automate power intent flows and analysis •Proficient in writing good quality, synthesizable RTL (Verilog/SystemVerilog), SoC integration, and UPF aware synthesis/implementation flows •Proficient understanding of C/C++, sufficient to review and interact with firmware power control sequences •Proven knowledge of retention (save/restore) cells, isolation cells, level shifters, power gating, and multi voltage domains •Strong familiarity with power analysis and verification tools (e.g., PowerArtist, PTPX, Calypto, CLP, VC LP)
Preferred: •Background coordinating PMIC interfaces and hardware firmware power sequencing •Experience defining retention/register re store sequences and retention IP integration •Exposure to post silicon validation, lab bring up of power state transitions, and diagnostic logging
Javier Leon Talent Acquisition Chelsea Search Group 619-227-3193 cell FJLrecruiter@gmail.com www.LinkedIn.com/in/JavierLeon (are we connected?)
Responsibilities •Conduct power modeling & analysis: use UPF driven flows for early RTL power budgeting, leakage/dynamic power estimation, DVFS schemes, gate level impact, and thermal aware power sequencing. •Coordinate cross team: align power intent integration, sequencing handshakes, API behavior, and cross domain safety with firmware, verification, RTL, physical design, and PMIC teams. •Define UPF/CPF power intent architecture: establish power domains, power states, retention policies, isolation strategies, and level shifter insertion across the SoC hierarchy. •Develop and implement advanced power management architecture-including Dynamic Voltage and Frequency Scaling (DVFS), power gating, and low power states-to enhance energy efficiency across SoC domains and use case •Micro-architect, Design and Develop power management unit for Next Gen AI accelerator chip •Partner with firmware teams: leverage knowledge of C/C++ to review and reason about firmware-controlled PMIC interactions, power state transitions, retention restore logic, and isolation control-without performing firmware development directly. •Specify structural low power elements: design isolation cells, level shifters, power switches, and retention (save/restore) flows to ensure correct behavior across power states. •Support low power verification: establish UPF aware testbench strategies, static and dynamic low power checks for EDA signoff, ensuring correct insertion of retention and isolation logic and domain handshakes. •Support silicon bring up: assist with post silicon validation of retention sequences, isolation logic, voltage transitions, and state handovers during lab bring up.
Requirements: •5+ years of experience in SoC low power architecture and flows, especially UPF/CPF intent specification •Bachelor's or Master's in EE, CE, or related technical field. •Experience with scripting (e.g., Python, Tcl, Perl) to automate power intent flows and analysis •Proficient in writing good quality, synthesizable RTL (Verilog/SystemVerilog), SoC integration, and UPF aware synthesis/implementation flows •Proficient understanding of C/C++, sufficient to review and interact with firmware power control sequences •Proven knowledge of retention (save/restore) cells, isolation cells, level shifters, power gating, and multi voltage domains •Strong familiarity with power analysis and verification tools (e.g., PowerArtist, PTPX, Calypto, CLP, VC LP)
Preferred: •Background coordinating PMIC interfaces and hardware firmware power sequencing •Experience defining retention/register re store sequences and retention IP integration •Exposure to post silicon validation, lab bring up of power state transitions, and diagnostic logging
Javier Leon Talent Acquisition Chelsea Search Group 619-227-3193 cell FJLrecruiter@gmail.com www.LinkedIn.com/in/JavierLeon (are we connected?)