Chelsea Search Group
Senior Network-on-Chip (NoC)/Fabric Engineer
Chelsea Search Group, San Jose, California, United States, 95199
Senior Network-on-Chip (NoC)/Fabric Engineer
US Citizen or US Permanent Resident
San Jose, California or remote from any US location
Responsibilities
• Architect the on-chip interconnect fabric for AI SoCs and/or chiplets, supporting high-throughput communication between compute, memory, DMA, and IO blocks.
• Define and model topology (mesh, ring, crossbar, hierarchical) and routing schemes for performance and scalability.
• Develop and maintain high-quality Verilog/SystemVerilog RTL for custom system interconnect fabrics; own full RTL design cycle including coding, integration of third-party IPs, synthesis readiness, and lint/sanity checks.
• Develop policies for flow control, congestion avoidance, and traffic prioritization (QoS) across heterogeneous traffic classes.
• Collaborate with compute, memory, and accelerator IP teams to define interface protocols (AXI, custom NoC) and bandwidth requirements.
• Perform performance modeling/analysis, simulation, and tradeoff analysis for latency, throughput, area, and power.
• Drive microarchitectural choices around buffer sizing, arbitration logic, reset schemes and clock gating.
• Partner with synthesis and verification teams to guide block-level implementation and testbench coverage.
• Support multi-chiplet and package-level interconnect strategies, including die-to-die fabrics, chiplet tiling, or optical/electrical bridges.
• Monitor technology trends (e.g., CXL, UALink, advanced packaging) and propose integration opportunities.
Requirements :
• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in SoC architecture, with 3+ years focused on NoC/Fabric design.
• Proficiency in Verilog/SystemVerilog with hands-on experience designing and integrating complex SoC subsystems, including bus fabrics and third-party IPs.
• Strong grasp of computer architecture, interconnect theory, and hardware dataflow.
• Hands-on understanding of bus protocols (AXI/APD/proprietary) and bus-level SoC integration.
• Solid knowledge of performance/power tradeoffs and congestion bottlenecks in complex SoC designs.
Desired :
• Experience building AI-specific SoCs, GPUs, or domain-specific accelerators.
• Exposure to chiplet interconnects, 2.5D/3D stacking, or EMIB/CoWoS.
• Familiarity with traffic modeling of ML workloads and how they influence NoC behavior.
• Experience with EDA tools for NoC synthesis, verification, and signoff.
• Proficiency in scripting (Python, Tcl) for automation and data analysis.
US Citizen or US Permanent Resident
San Jose, California or remote from any US location
Responsibilities
• Architect the on-chip interconnect fabric for AI SoCs and/or chiplets, supporting high-throughput communication between compute, memory, DMA, and IO blocks.
• Define and model topology (mesh, ring, crossbar, hierarchical) and routing schemes for performance and scalability.
• Develop and maintain high-quality Verilog/SystemVerilog RTL for custom system interconnect fabrics; own full RTL design cycle including coding, integration of third-party IPs, synthesis readiness, and lint/sanity checks.
• Develop policies for flow control, congestion avoidance, and traffic prioritization (QoS) across heterogeneous traffic classes.
• Collaborate with compute, memory, and accelerator IP teams to define interface protocols (AXI, custom NoC) and bandwidth requirements.
• Perform performance modeling/analysis, simulation, and tradeoff analysis for latency, throughput, area, and power.
• Drive microarchitectural choices around buffer sizing, arbitration logic, reset schemes and clock gating.
• Partner with synthesis and verification teams to guide block-level implementation and testbench coverage.
• Support multi-chiplet and package-level interconnect strategies, including die-to-die fabrics, chiplet tiling, or optical/electrical bridges.
• Monitor technology trends (e.g., CXL, UALink, advanced packaging) and propose integration opportunities.
Requirements :
• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in SoC architecture, with 3+ years focused on NoC/Fabric design.
• Proficiency in Verilog/SystemVerilog with hands-on experience designing and integrating complex SoC subsystems, including bus fabrics and third-party IPs.
• Strong grasp of computer architecture, interconnect theory, and hardware dataflow.
• Hands-on understanding of bus protocols (AXI/APD/proprietary) and bus-level SoC integration.
• Solid knowledge of performance/power tradeoffs and congestion bottlenecks in complex SoC designs.
Desired :
• Experience building AI-specific SoCs, GPUs, or domain-specific accelerators.
• Exposure to chiplet interconnects, 2.5D/3D stacking, or EMIB/CoWoS.
• Familiarity with traffic modeling of ML workloads and how they influence NoC behavior.
• Experience with EDA tools for NoC synthesis, verification, and signoff.
• Proficiency in scripting (Python, Tcl) for automation and data analysis.