Samsung Semiconductor
Micro-Architect/Logic Designer (Memory Controller)
Samsung Semiconductor, San Jose, California, United States, 95199
Position
Micro-Architect/Logic Designer (Memory Controller) Join to apply for the
Micro-Architect/Logic Designer (Memory Controller)
role at
Samsung Semiconductor Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role And Responsibilities
As a Sr. Memory Controller Micro-Architect/Logic Designer, you will contribute to the micro-architecture development and logic design of our advanced custom memory controller for LPDDR5/6. This is a senior level role where you will interact with the system architects, verification, performance/power and design implementation teams. You will own and drive the critical memory controller related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. Drive timely development and debugging of new features for the custom memory controller. Work on SOC IP delivery with all sanity checks. Perform timing debug and closure. Work on LINT, CDC flows and analysis. Work on power analysis flows and power analysis. Experience with ECO flows. Collaborate with the verification team to verify functionality and correctness of the design. Communicate with implementation to achieve timing and area goals. Produce high-quality RTL on schedule meeting PPA goals. Engage with performance and power teams to achieve performance and power goals. Partner with the physical design and CAD teams to resolve implementation level details. Skills And Qualifications
15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years with a Master’s Degree, or 11+ years with a PhD Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs Experience with memory controller architecture on LPDDR5/6, GDDR, PIM, HBM Demonstrated experience from architectural design through RTL design on high performance digital designs Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO Knowledge of JEDEC memory standards preferred Understanding of interface protocols such as AMBA, AXI, ACE is desired Knowledge of AES, ECC, RAS features preferred Strong communication and interpersonal skills; ability to work in a dynamic, global team Experience with a scripting language like Perl or Python Energetic, curious, and passionate about logic design Our Team
Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. We focus on delivering system modeling capability based on optimization and use-case-driven analysis to enable a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products for multiple market segments. You will be part of a diverse, collaborative, and supportive environment where you will learn and help shape the team’s culture. Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package. The base pay range for this role is between $174,557 and $305,414. Your actual base pay will depend on variables such as education, skills, qualifications, experience, and work location. Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more. In addition, regular full-time employees are eligible for MBO bonus compensation based on company, division, and individual performance. This role might be eligible to participate in long term incentive plan and relocation. U.S. Export Control
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets
By submitting an application, you agree not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information belonging to any current or previous employer or other person or entity. Equal Employment Opportunity
Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, disability, or any other characteristic protected by law. Job Details
Seniority level: Mid-Senior level Employment type: Full-time Job function: Design, Art/Creative, and Information Technology Industries: Computers and Electronics Manufacturing Referrals increase your chances of interviewing at Samsung Semiconductor. Get notified about new Architect jobs in San Jose, CA.
#J-18808-Ljbffr
Micro-Architect/Logic Designer (Memory Controller) Join to apply for the
Micro-Architect/Logic Designer (Memory Controller)
role at
Samsung Semiconductor Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role And Responsibilities
As a Sr. Memory Controller Micro-Architect/Logic Designer, you will contribute to the micro-architecture development and logic design of our advanced custom memory controller for LPDDR5/6. This is a senior level role where you will interact with the system architects, verification, performance/power and design implementation teams. You will own and drive the critical memory controller related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. Drive timely development and debugging of new features for the custom memory controller. Work on SOC IP delivery with all sanity checks. Perform timing debug and closure. Work on LINT, CDC flows and analysis. Work on power analysis flows and power analysis. Experience with ECO flows. Collaborate with the verification team to verify functionality and correctness of the design. Communicate with implementation to achieve timing and area goals. Produce high-quality RTL on schedule meeting PPA goals. Engage with performance and power teams to achieve performance and power goals. Partner with the physical design and CAD teams to resolve implementation level details. Skills And Qualifications
15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years with a Master’s Degree, or 11+ years with a PhD Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs Experience with memory controller architecture on LPDDR5/6, GDDR, PIM, HBM Demonstrated experience from architectural design through RTL design on high performance digital designs Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO Knowledge of JEDEC memory standards preferred Understanding of interface protocols such as AMBA, AXI, ACE is desired Knowledge of AES, ECC, RAS features preferred Strong communication and interpersonal skills; ability to work in a dynamic, global team Experience with a scripting language like Perl or Python Energetic, curious, and passionate about logic design Our Team
Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. We focus on delivering system modeling capability based on optimization and use-case-driven analysis to enable a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products for multiple market segments. You will be part of a diverse, collaborative, and supportive environment where you will learn and help shape the team’s culture. Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package. The base pay range for this role is between $174,557 and $305,414. Your actual base pay will depend on variables such as education, skills, qualifications, experience, and work location. Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more. In addition, regular full-time employees are eligible for MBO bonus compensation based on company, division, and individual performance. This role might be eligible to participate in long term incentive plan and relocation. U.S. Export Control
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets
By submitting an application, you agree not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information belonging to any current or previous employer or other person or entity. Equal Employment Opportunity
Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, disability, or any other characteristic protected by law. Job Details
Seniority level: Mid-Senior level Employment type: Full-time Job function: Design, Art/Creative, and Information Technology Industries: Computers and Electronics Manufacturing Referrals increase your chances of interviewing at Samsung Semiconductor. Get notified about new Architect jobs in San Jose, CA.
#J-18808-Ljbffr