Intel
About the RoleWe are looking for senior technology leader who is familiar with advanced process nodes (sub 3nm) and have successfully exercised RTL to GDS flows to tape-out (tape-in) to the foundry.The Senior Design Engineer performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
ResponsibilitiesTake a design (block, subsystem or SoC) RTL through full scope of physical design (synthesis, floorplan, P&R and signoff) for tape-out (tape-in)Work with front end design team to tweak RTL or design to improve the PPAWork with Design Foundry Technology team to arrive at appropriate test planUnderstand how the SoC will be assembled in the package that will drive the top level & block level floorplan
Required Background and Experience:Hands-on experience with industry standard EDA tools both construction & signoff and be able to help junior engineers in the groupStrong technical experience in designing complex SoC, CPU & GPU cores using advanced process nodesAbility to understand fabless customer requirements including end market applications and synthesize them to our offerings to derive an acceptable solutionExperience in successfully managing customer engagement
Qualifications:Bachelor’s degree in electrical engineering or applied sciences. Master’s or PhD preferred15+ years of demonstrated organizational and technical leadership with a proven track record of working well in a matrixed organization
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, Texas, Austin
Additional Locations:US, California, Santa Clara; US, Oregon, Hillsboro
Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.
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