Insight Global
Overview We are looking for an Optoelectronics Packaging Design Engineer to design and develop our IC packaging solutions. We are seeking an adaptable, well-organized engineer who can work between hardware, manufacturing, systems, IC and operations to drive our packaging development. The role is San Francisco based and will include some travel.
Want to apply Read all the information about this position below, then hit the apply button. Base pay range: $170,000.00/yr - $200,000.00/yr. This range is provided by Insight Global. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Responsibilities
Lead the design, simulation, and development of high-performance IC package designs and chip carriers to meet product and qualification requirements. Own each IC package end-to-end. Work closely with hardware engineering disciplines to design best-in-class package assemblies for advanced laser and opto-electronic ASIC chips operating in harsh environments. Collaborate with manufacturing engineering and quality teams to ensure a seamless transition from prototype to high-volume production. Define and execute test plans for package/system level reliability. Conduct failure analysis to drive continuous improvement. Manage vendors, including sourcing, vetting, quoting, design for manufacturing (DFM), and low-volume order placement of diverse components such as substrates, epoxies, coated glass, PCBAs, and tooling. Required skills and experience
5+ years in Semiconductor Package/Process Development or 2+ years with a relevant master’s degree. Proficiency in 3D CAD (e.g., SolidWorks) and FEA simulation tools (e.g., ANSYS). Hands-on experience with automated high-accuracy die bonding, wirebonding, and active optical alignment systems. Experience with multi-layer ceramic, CMOS image sensor, BGA packages, and organic substrates. Experience in wafer-level processing (dielectric thin film deposition, RIE silicon processing, wafer-to-wafer bonding, spin coat/lift-off processing, wafer dice and test). Working knowledge of Failure Analysis tools such as X-ray, 3D interferometry, DIC microscopy, SEM, cross-section, destructive testing, etc. Experience with optical systems (LiDAR, camera, microscope, etc.). Employment details
Permanent full-time position with competitive and comprehensive benefits (medical, dental, and vision); 401(k); company-paid holidays; paid sick leave and vacation; stock options. Base salary range $130-$200K. Candidate will need to be comfortable working fully onsite in the San Francisco office. Seniority level
Mid-Senior level
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Want to apply Read all the information about this position below, then hit the apply button. Base pay range: $170,000.00/yr - $200,000.00/yr. This range is provided by Insight Global. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Responsibilities
Lead the design, simulation, and development of high-performance IC package designs and chip carriers to meet product and qualification requirements. Own each IC package end-to-end. Work closely with hardware engineering disciplines to design best-in-class package assemblies for advanced laser and opto-electronic ASIC chips operating in harsh environments. Collaborate with manufacturing engineering and quality teams to ensure a seamless transition from prototype to high-volume production. Define and execute test plans for package/system level reliability. Conduct failure analysis to drive continuous improvement. Manage vendors, including sourcing, vetting, quoting, design for manufacturing (DFM), and low-volume order placement of diverse components such as substrates, epoxies, coated glass, PCBAs, and tooling. Required skills and experience
5+ years in Semiconductor Package/Process Development or 2+ years with a relevant master’s degree. Proficiency in 3D CAD (e.g., SolidWorks) and FEA simulation tools (e.g., ANSYS). Hands-on experience with automated high-accuracy die bonding, wirebonding, and active optical alignment systems. Experience with multi-layer ceramic, CMOS image sensor, BGA packages, and organic substrates. Experience in wafer-level processing (dielectric thin film deposition, RIE silicon processing, wafer-to-wafer bonding, spin coat/lift-off processing, wafer dice and test). Working knowledge of Failure Analysis tools such as X-ray, 3D interferometry, DIC microscopy, SEM, cross-section, destructive testing, etc. Experience with optical systems (LiDAR, camera, microscope, etc.). Employment details
Permanent full-time position with competitive and comprehensive benefits (medical, dental, and vision); 401(k); company-paid holidays; paid sick leave and vacation; stock options. Base salary range $130-$200K. Candidate will need to be comfortable working fully onsite in the San Francisco office. Seniority level
Mid-Senior level
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