Qualcomm
Enablement Engineer, On-chip power delivery, Staff
Qualcomm, San Diego, California, United States, 92189
Company:
Qualcomm Technologies, Inc. Job Area:
Engineering Group, Engineering Group > ASICS Engineering General Summary:
Qualcomm has a position in San Diego, CA, focusing on on-chip power grid optimization for sub 2nm nodes. The role involves driving 3D system integration, balancing performance and cost, and includes responsibilities such as integrated VRs and backside power delivery. Ideal candidates should have a background in 2.5D/3D on-chip integration, process technology, and design enablement. Responsibilities include: Develop power grid structure for key IPs (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance Provide design solutions for IR/EM and routing optimization Work with process team for process tuning to achieve better PDN (Power Delivery Network) design Support advanced process node PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out Provide guidance to PnR (Place and Route) designer on PDN issue fixing Drive backside power delivery solution balancing performance and cost Job Qualifications:
Master of Science in Electrical Engineering or above Deep understanding of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis Programming skills, such as Python, Matlab for automation, data analysis, and results summary Knowledge of digital design PnR from floorplan stage and IP placement Knowledge of digital design PnR flow Being familiar with SPICE Good communication skills Qualcomm is the world leader in wireless chipsets powering the majority of 4G and 5G devices, the largest fabless semiconductor in the world, and is widely regarded as one of the most employee friendly companies in the high-tech marketplace. Qualcomm central hardware system (CHS) team has a broad array of responsibilities that include developing cutting edge package technology, developing system-level power and signal integrity from transistor to PMIC on a wide range of products used by millions customers. Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. EEO Employer:
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits:
$140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We offer a competitive annual discretionary bonus program and potential for RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). Our benefits package supports success at work, home, and at play. Your recruiter can discuss details about Qualcomm's benefits. If you would like more information about this role, please contact Qualcomm Careers.
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Qualcomm Technologies, Inc. Job Area:
Engineering Group, Engineering Group > ASICS Engineering General Summary:
Qualcomm has a position in San Diego, CA, focusing on on-chip power grid optimization for sub 2nm nodes. The role involves driving 3D system integration, balancing performance and cost, and includes responsibilities such as integrated VRs and backside power delivery. Ideal candidates should have a background in 2.5D/3D on-chip integration, process technology, and design enablement. Responsibilities include: Develop power grid structure for key IPs (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance Provide design solutions for IR/EM and routing optimization Work with process team for process tuning to achieve better PDN (Power Delivery Network) design Support advanced process node PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out Provide guidance to PnR (Place and Route) designer on PDN issue fixing Drive backside power delivery solution balancing performance and cost Job Qualifications:
Master of Science in Electrical Engineering or above Deep understanding of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis Programming skills, such as Python, Matlab for automation, data analysis, and results summary Knowledge of digital design PnR from floorplan stage and IP placement Knowledge of digital design PnR flow Being familiar with SPICE Good communication skills Qualcomm is the world leader in wireless chipsets powering the majority of 4G and 5G devices, the largest fabless semiconductor in the world, and is widely regarded as one of the most employee friendly companies in the high-tech marketplace. Qualcomm central hardware system (CHS) team has a broad array of responsibilities that include developing cutting edge package technology, developing system-level power and signal integrity from transistor to PMIC on a wide range of products used by millions customers. Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. EEO Employer:
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits:
$140,000.00 - $210,000.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We offer a competitive annual discretionary bonus program and potential for RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). Our benefits package supports success at work, home, and at play. Your recruiter can discuss details about Qualcomm's benefits. If you would like more information about this role, please contact Qualcomm Careers.
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