SPACE EXPLORATION TECHNOLOGIES CORP
ASIC/SOC DFT Engineer (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Sunnyvale, California, United States, 94087
Overview
Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SpaceX is deploying Starlink, the world’s most advanced broadband internet system, to provide fast, reliable internet globally. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers, and the software that brings it all together. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips will enable connectivity in places previously unavailable, unaffordable, or unreliable, helping to expand Starlink’s performance and capabilities. Responsibilities
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Run and evaluate scan insertion through synthesis tools and refine scan insertion recipe for maximum coverage Run ATPG (Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals Run and debug non-timing and SDF annotated gate-level simulations Create ATPG content for post-silicon testing and validate content through gate-level simulation Collaborate with circuit physical design, ATPG, and manufacturing teams to facilitate high-quality scan coverage in silicon Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 1+ years of professional experience working with ASICs Experience in scan insertion or DFT setup Preferred Skills and Experience
Understanding of ASIC design flow, methodologies, physical design, and verification Experience with high reliability design and implementations Familiar with Verilog/SystemVerilog Familiar with UPF (unified power format), formal verification, and DRC rule checking Ability to work in a dynamic environment with changing needs and requirements Team-player with a can-do attitude, able to contribute in a group while working independently Enjoys learning new skills and taking on challenges Additional Requirements
Must be willing to work extended hours and weekends as needed Compensation and Benefits
Pay range: Design Verification Engineer/Level I: $130,000 - $155,000 per year; Design Verification Engineer/Level II: $150,000 - $180,000 per year. Your actual level and base salary will be determined on a case-by-case basis based on job-related knowledge, education, and experience. Base salary is part of SpaceX’s total rewards package, which may include long-term incentives, stock options, discretionary bonuses, and the ability to purchase additional stock through an Employee Stock Purchase Plan. Benefits include medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, and paid time off. Exempt employees are eligible for 5 days of sick leave per year and may accrue 3 weeks of paid vacation plus 10+ paid holidays per year. Legal and Equal Opportunity
SpaceX is an Equal Opportunity Employer; employment is based on merit, competence, and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. We comply with ITAR and export regulations where applicable. To view SpaceX’s Affirmative Action Plan or request reasonable accommodation, contact EEOCompliance@spacex.com.
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Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SpaceX is deploying Starlink, the world’s most advanced broadband internet system, to provide fast, reliable internet globally. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers, and the software that brings it all together. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips will enable connectivity in places previously unavailable, unaffordable, or unreliable, helping to expand Starlink’s performance and capabilities. Responsibilities
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Run and evaluate scan insertion through synthesis tools and refine scan insertion recipe for maximum coverage Run ATPG (Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals Run and debug non-timing and SDF annotated gate-level simulations Create ATPG content for post-silicon testing and validate content through gate-level simulation Collaborate with circuit physical design, ATPG, and manufacturing teams to facilitate high-quality scan coverage in silicon Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 1+ years of professional experience working with ASICs Experience in scan insertion or DFT setup Preferred Skills and Experience
Understanding of ASIC design flow, methodologies, physical design, and verification Experience with high reliability design and implementations Familiar with Verilog/SystemVerilog Familiar with UPF (unified power format), formal verification, and DRC rule checking Ability to work in a dynamic environment with changing needs and requirements Team-player with a can-do attitude, able to contribute in a group while working independently Enjoys learning new skills and taking on challenges Additional Requirements
Must be willing to work extended hours and weekends as needed Compensation and Benefits
Pay range: Design Verification Engineer/Level I: $130,000 - $155,000 per year; Design Verification Engineer/Level II: $150,000 - $180,000 per year. Your actual level and base salary will be determined on a case-by-case basis based on job-related knowledge, education, and experience. Base salary is part of SpaceX’s total rewards package, which may include long-term incentives, stock options, discretionary bonuses, and the ability to purchase additional stock through an Employee Stock Purchase Plan. Benefits include medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, and paid time off. Exempt employees are eligible for 5 days of sick leave per year and may accrue 3 weeks of paid vacation plus 10+ paid holidays per year. Legal and Equal Opportunity
SpaceX is an Equal Opportunity Employer; employment is based on merit, competence, and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. We comply with ITAR and export regulations where applicable. To view SpaceX’s Affirmative Action Plan or request reasonable accommodation, contact EEOCompliance@spacex.com.
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