Highbrow
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Job Title: C Programmer Telecom Domain
- Location: Atlanta, GA
- Employment type: Full-time
- Seniority level: Mid-Senior level
Key Responsibilities
- Develop, debug, and optimize C-based telecom components: L1/L2/L3 stacks, signaling, media handling, billing, or messaging systems.
- Implement and enhance network protocols (TCP/IP, SIP, RTP, Diameter, NGAP/S1AP3GPP).
- Write modular, reusable, and efficient C code; manage memory manually to avoid leaks and buffer issues.
- Use debugging tools (GDB, Valgrind), static analyzers (Coverity, Cppcheck), and trace signal flows to troubleshoot complex issues.
- Collaborate in Agile/scrum environmentsplan, code, test features, participate in design/code reviews, and deliver high-quality software on time.
- Produce technical documentation: software design specs, interface definitions, test plans.
- Work cross-functionally with hardware, firmware, testing, QA, and system engineering teams.
Qualifications
Required:
- Bachelors (or higher) in Computer Science, Electrical/Electronics Engineering, Telecom, or related field.
- 3+ years of professional experience in C (C99/C11), especially for performance-critical or telecom systems.
- In-depth understanding of telecom protocols: 3GPP 4G/5G stacks, SIP/H.323, SS7, Diameter, RTP, TCP/IP.
- Strong Linux-based development experience, including IPC, POSIX threads, build tools (Make/CMake), version control (Git).
- Solid debugging skills and familiarity with GDB, Valgrind, trace tools.
- Good problem-solving ability and communication skillsable to work in distributed teams.
Preferred:
- Telecom-specific knowledge: L2/L3 control plane, OAM (e.g., IEEE 802.1ag, Y.1731), RAN/cloud integration.
- Experience with embedded systems or real-time OS (Linux kernel, RTOS).
- Exposure to cloud-native technologies (Docker, Kubernetes), automation scripting (Python, Go).
- Familiarity with test tools (Ixia/Spirent), telecom benchmarking standards (RFC 2544), and static analysis/security compliance.
- Background in DSP, codecs, hardware interfaces, FPGA/ASIC integration.
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