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Samsung Semiconductor

Senior Staff Engineer

Samsung Semiconductor, San Jose, California, United States, 95199

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Digital Design and Verification Engineer

Looking for a Formal verification engineer with hands-on experience in development of FPV, DPV, AEP & SEQ Formal Techniques, expertise in System Verilog Assertion/Properties to join my team at San Jose, CA or Austin, TX. Overview

Role focused on formal verification for digital design projects. Location options: San Jose, CA or Austin, TX. Responsibilities

Mandatory experience in Formal Verification - 3 Years Minimum. Preferably a Post Graduate. Develop formal verification setup using System Verilog modules and Assertions. Run formal verification checks, analyze the results, and debug any issues. Develop and enhance constraints, checks, and cover points to achieve verification quality. Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions. Seniority level

Mid-Senior level Employment type

Full-time Job function

Engineering and Information Technology Semiconductor Manufacturing Direct message the job poster from Samsung Semiconductor to apply.

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