Celestial A
Senior SoC Design Engineer Santa Clara, CA; Orange County, CA
Celestial A, Santa Clara, California, us, 95053
Overview
We are seeking a
Senior SoC Design Engineer
to contribute to the design, integration, and implementation of complex System-on-Chips (SoCs). This role involves hands-on work with high-speed interconnects, IP integration, and the full ASIC implementation flow. You will own the micro-architecture, RTL design, and synthesis, working closely with verification and the physical design team. We are looking for strong experience in SoC integration, high-speed interfaces, or ASIC implementation.
Essential Duties and Responsibilities
SoC Design & IP Integration:
Integrate and configure high-speed IPs (e.g., UCIe, CXL, PCIe, Serdes) into SoC designs.
Define and integrate AXI-based Network-on-Chip (NoC) interconnects and subsystems.
Collaborate effectively with cross-functional teams, including IP vendors, verification, and physical design, to ensure seamless integration and debug.
ASIC Implementation & Sign-off:
Create the micro-architecture, RTL design, synthesis, and be responsible for design quality (Lint, CDC, and RDC).
Optimize RTL for power, performance, and area (PPA) goals.
Verification & Debug:
Work with pre-silicon verification teams to ensure design is verified.
Provide inputs for the test plan covering functionality, corner cases, functional coverage.
Run tests and debug, work with the verification team to close coverage, resolve design, timing, and protocol compliance issues in close collaboration with verification and firmware teams.
Participate in post-silicon bring-up and debug efforts.
Support emulation and FPGA-based prototyping for early IP validation.
Qualifications
Education & Experience:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years
of hands-on experience in ASIC/SoC design, integration, and implementation.
Technical Expertise:
SoC Design & RTL:
Strong experience in RTL design and integration using Verilog/SystemVerilog.
Experience working with interconnect protocols like AXI.
Experience integrating high-speed interfaces (e.g., UCIe, CXL, PCIe, DDR).
ASIC Implementation:
Hands-on experience with logic synthesis, static timing analysis (STA), and low-power design techniques.
Proficiency with common EDA tools for synthesis and STA.
Knowledge of physical design constraints, floorplanning, and the timing closure flow.
Verification & Debug:
Familiarity with pre-silicon verification methodologies (e.g., UVM).
Strong problem-solving skills with a methodical approach to debugging.
Familiarity with post-silicon bring-up and debug techniques is a plus.
Scripting:
Proficiency in scripting languages like Tcl or Python for automation and debug.
Preferred Qualifications
Experience working with UCIe/CXL/PCIe/Serdes would be a plus for this role.
Location Santa Clara, CA, or Orange County, CA
Compensation and Benefits As an early stage startup, we offer a competitive total compensation package including base salary, bonus, and equity. The target base salary for this role is approximately $185,000.00 - $215,000.00, with final offers based on depth of experience and skills demonstrated in the interview process. We offer health, vision, dental, and life insurance, and a collaborative, learning-oriented work environment.
Celestial AI Inc. is proud to be an equal opportunity workplace and an affirmative action employer.
#J-18808-Ljbffr
We are seeking a
Senior SoC Design Engineer
to contribute to the design, integration, and implementation of complex System-on-Chips (SoCs). This role involves hands-on work with high-speed interconnects, IP integration, and the full ASIC implementation flow. You will own the micro-architecture, RTL design, and synthesis, working closely with verification and the physical design team. We are looking for strong experience in SoC integration, high-speed interfaces, or ASIC implementation.
Essential Duties and Responsibilities
SoC Design & IP Integration:
Integrate and configure high-speed IPs (e.g., UCIe, CXL, PCIe, Serdes) into SoC designs.
Define and integrate AXI-based Network-on-Chip (NoC) interconnects and subsystems.
Collaborate effectively with cross-functional teams, including IP vendors, verification, and physical design, to ensure seamless integration and debug.
ASIC Implementation & Sign-off:
Create the micro-architecture, RTL design, synthesis, and be responsible for design quality (Lint, CDC, and RDC).
Optimize RTL for power, performance, and area (PPA) goals.
Verification & Debug:
Work with pre-silicon verification teams to ensure design is verified.
Provide inputs for the test plan covering functionality, corner cases, functional coverage.
Run tests and debug, work with the verification team to close coverage, resolve design, timing, and protocol compliance issues in close collaboration with verification and firmware teams.
Participate in post-silicon bring-up and debug efforts.
Support emulation and FPGA-based prototyping for early IP validation.
Qualifications
Education & Experience:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years
of hands-on experience in ASIC/SoC design, integration, and implementation.
Technical Expertise:
SoC Design & RTL:
Strong experience in RTL design and integration using Verilog/SystemVerilog.
Experience working with interconnect protocols like AXI.
Experience integrating high-speed interfaces (e.g., UCIe, CXL, PCIe, DDR).
ASIC Implementation:
Hands-on experience with logic synthesis, static timing analysis (STA), and low-power design techniques.
Proficiency with common EDA tools for synthesis and STA.
Knowledge of physical design constraints, floorplanning, and the timing closure flow.
Verification & Debug:
Familiarity with pre-silicon verification methodologies (e.g., UVM).
Strong problem-solving skills with a methodical approach to debugging.
Familiarity with post-silicon bring-up and debug techniques is a plus.
Scripting:
Proficiency in scripting languages like Tcl or Python for automation and debug.
Preferred Qualifications
Experience working with UCIe/CXL/PCIe/Serdes would be a plus for this role.
Location Santa Clara, CA, or Orange County, CA
Compensation and Benefits As an early stage startup, we offer a competitive total compensation package including base salary, bonus, and equity. The target base salary for this role is approximately $185,000.00 - $215,000.00, with final offers based on depth of experience and skills demonstrated in the interview process. We offer health, vision, dental, and life insurance, and a collaborative, learning-oriented work environment.
Celestial AI Inc. is proud to be an equal opportunity workplace and an affirmative action employer.
#J-18808-Ljbffr