Mindlance
Performance Modeling/Verification Engineer - Intermediate (US)
Mindlance, Santa Clara, California, us, 95053
JOB DUTIES:
Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
Collaborate with cross teams to integrate models into tools used for system-level designs, ensuring proper functionality and performance.
Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Create clear and comprehensive documentation for models, including usage guidelines and design specifications.
Deliverables: Cycle approximate performance models
SV/UVM Functional and Performance Verification
EXPERIENCE AND EDUCATION: 5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ;Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills; PCIe & AXI Knowledge Preferred
Collaborate with cross teams to integrate models into tools used for system-level designs, ensuring proper functionality and performance.
Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Create clear and comprehensive documentation for models, including usage guidelines and design specifications.
Deliverables: Cycle approximate performance models
SV/UVM Functional and Performance Verification
EXPERIENCE AND EDUCATION: 5 or more years of proven modeling & verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; Strong background in C/C++ development in a Linux Environment; Strong debug skills and experience with debug tools such as Gdb, Valgrind ;Knowledge of Perl and Makefiles; Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills; PCIe & AXI Knowledge Preferred