SPACE EXPLORATION TECHNOLOGIES CORP
Physical Design Engineer II (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Sunnyvale, California, United States, 94087
Overview
Physical Design Engineer II (Silicon Engineering) Sunnyvale, CA SpaceX was founded with the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. SpaceX is actively developing technologies to enable human life on Mars and to deploy Starlink, the worlds most advanced broadband internet system. We design, build, test, and operate all parts of the system thousands of satellites, consumer receivers, and the software that brings it all together. We are seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures, enabling connectivity in places previously unavailable, affordable, or reliable. Responsibilities Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Basic Qualifications
Bachelors degree in electrical engineering, computer engineering or computer science 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development
Preferred Skills and Experience
Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Understanding of CMOS digital design principles, standard cells their functionality, and standard cell libraries Understanding of CMOS power dissipation in deep submicron processes (leakage/dynamic) Familiar with CMOS analog circuit and physical design Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows Self-driven with a can-do attitude, willing to learn, and able to work in a dynamic group environment
Additional Requirements
Must be willing to work extended hours and weekends as needed
Compensation and Benefits
Pay range: Physical Design Engineer/Level II: $150,000.00 - $180,000.00 per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on job-related knowledge and skills, education, and experience. Base salary is one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives (stock or stock options), discretionary bonuses, and stock purchase opportunities. You will have access to comprehensive medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, paid vacation and holidays, and sick leave for exempt employees. Equal Opportunity and Compliance
SpaceX is an Equal Opportunity Employer; employment is based on merit, competence and qualifications and is not influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. Applicants requiring reasonable accommodation to the application/interview process should contact EEOCompliance@spacex.com. #J-18808-Ljbffr
Physical Design Engineer II (Silicon Engineering) Sunnyvale, CA SpaceX was founded with the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. SpaceX is actively developing technologies to enable human life on Mars and to deploy Starlink, the worlds most advanced broadband internet system. We design, build, test, and operate all parts of the system thousands of satellites, consumer receivers, and the software that brings it all together. We are seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures, enabling connectivity in places previously unavailable, affordable, or reliable. Responsibilities Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Basic Qualifications
Bachelors degree in electrical engineering, computer engineering or computer science 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development
Preferred Skills and Experience
Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Understanding of CMOS digital design principles, standard cells their functionality, and standard cell libraries Understanding of CMOS power dissipation in deep submicron processes (leakage/dynamic) Familiar with CMOS analog circuit and physical design Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows Self-driven with a can-do attitude, willing to learn, and able to work in a dynamic group environment
Additional Requirements
Must be willing to work extended hours and weekends as needed
Compensation and Benefits
Pay range: Physical Design Engineer/Level II: $150,000.00 - $180,000.00 per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on job-related knowledge and skills, education, and experience. Base salary is one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives (stock or stock options), discretionary bonuses, and stock purchase opportunities. You will have access to comprehensive medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, paid vacation and holidays, and sick leave for exempt employees. Equal Opportunity and Compliance
SpaceX is an Equal Opportunity Employer; employment is based on merit, competence and qualifications and is not influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. Applicants requiring reasonable accommodation to the application/interview process should contact EEOCompliance@spacex.com. #J-18808-Ljbffr