Astera Labs
Senior Firmware Engineer – CXL Memory Solutions
Astera Labs, San Jose, California, United States, 95199
Senior Firmware Engineer – CXL Memory Solutions
San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Astera Labs is seeking a highly experienced
Senior Firmware Engineer
to lead the design and development of embedded firmware for cutting-edge
CXL memory expansion products
tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. Required Experience: Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field. 5+ years of hands-on experience in embedded firmware development using C. Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation. Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C. Key Responsibilities & Skills: Lead post-silicon bring-up and validation of PCIe/CXL/DDR interfaces at PHY and Link layers. Interpret technical specifications and develop robust, low-level C code in RTOS environments. Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations. Strong debugging skills and ability to triage and resolve issues in complex embedded systems. Familiarity with server I/O and memory workflows, performance tuning for latency and bandwidth optimization is a plus. Experience with pre-silicon validation in emulation environments is highly desirable. The base salary range is $175,750 USD – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Astera Labs is seeking a highly experienced
Senior Firmware Engineer
to lead the design and development of embedded firmware for cutting-edge
CXL memory expansion products
tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. Required Experience: Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field. 5+ years of hands-on experience in embedded firmware development using C. Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation. Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C. Key Responsibilities & Skills: Lead post-silicon bring-up and validation of PCIe/CXL/DDR interfaces at PHY and Link layers. Interpret technical specifications and develop robust, low-level C code in RTOS environments. Collaborate effectively with cross-functional teams and external partners to deliver weekly firmware releases and feature demonstrations. Strong debugging skills and ability to triage and resolve issues in complex embedded systems. Familiarity with server I/O and memory workflows, performance tuning for latency and bandwidth optimization is a plus. Experience with pre-silicon validation in emulation environments is highly desirable. The base salary range is $175,750 USD – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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