Amazon Web Services (AWS)
Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Amazon Web Services (AWS), Austin, Texas, us, 78716
Overview
Sr. DFT Design Engineer, AWS Machine Learning Acceleration role at Amazon Web Services (AWS). Description: AWS Utility Computing (UC) provides product innovations, supporting Compute, Database, Storage, IoT, Platform, and Productivity Apps services in AWS, including security solutions for cloud services. Annapurna Labs designs silicon and software that accelerates innovation, delivering custom chips, accelerators, and software stacks for large-scale deployments. As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in applying new technologies to large-scale server deployments and work with thought leaders across multiple technology areas. We expect relentlessly high standards and continuous improvement of product performance, quality, and cost. Responsibilities
Develop, implement and verify state-of-the-art Design for Test (DFT) architectures Work with block designers to integrate DFT implementations Collaborate with the physical design team to set up and implement DFT insertion flow Develop high-coverage and cost-effective DFT methodologies Perform RTL coding and verification Participate in silicon debugging and write scripts to handle ATE-related data Communicate and collaborate with team members across multiple disciplines Basic Qualifications
BS degree in EE, CE, or CS 5+ years of practical DFT experience with large processor and/or SoC designs Knowledge of industry-standard DFT tools and practices (ATPG, JTAG, MBIST) and trade-offs between test quality and test time Experience with automation script development Preferred Qualifications
MS degree in EE, CE or CS Broad knowledge of chip design from micro-architecture through physical design Experience with design verification (DV) simulation methodologies Experience with large gate-level simulation setup and debug with SDF Strong programming/scripting skills in Perl, Python or Tcl Experience with standard DFT/SCAN/ATPG tools and STA constraints for DFT modes Practical experience with silicon debug Equal Opportunity Employer notice: Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. If you require a workplace accommodation during the application or hiring process, please visit the accommodations information page for more details. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects cost of labor across several US geographic markets. Base pay ranges cited are for example purposes and may vary based on location, knowledge, skills, and experience. Amazon is a total compensation company and may offer equity, sign-on payments, and other benefits as part of a complete package. Company: Annapurna Labs (U.S.) Inc. Job ID: A3091748
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Sr. DFT Design Engineer, AWS Machine Learning Acceleration role at Amazon Web Services (AWS). Description: AWS Utility Computing (UC) provides product innovations, supporting Compute, Database, Storage, IoT, Platform, and Productivity Apps services in AWS, including security solutions for cloud services. Annapurna Labs designs silicon and software that accelerates innovation, delivering custom chips, accelerators, and software stacks for large-scale deployments. As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in applying new technologies to large-scale server deployments and work with thought leaders across multiple technology areas. We expect relentlessly high standards and continuous improvement of product performance, quality, and cost. Responsibilities
Develop, implement and verify state-of-the-art Design for Test (DFT) architectures Work with block designers to integrate DFT implementations Collaborate with the physical design team to set up and implement DFT insertion flow Develop high-coverage and cost-effective DFT methodologies Perform RTL coding and verification Participate in silicon debugging and write scripts to handle ATE-related data Communicate and collaborate with team members across multiple disciplines Basic Qualifications
BS degree in EE, CE, or CS 5+ years of practical DFT experience with large processor and/or SoC designs Knowledge of industry-standard DFT tools and practices (ATPG, JTAG, MBIST) and trade-offs between test quality and test time Experience with automation script development Preferred Qualifications
MS degree in EE, CE or CS Broad knowledge of chip design from micro-architecture through physical design Experience with design verification (DV) simulation methodologies Experience with large gate-level simulation setup and debug with SDF Strong programming/scripting skills in Perl, Python or Tcl Experience with standard DFT/SCAN/ATPG tools and STA constraints for DFT modes Practical experience with silicon debug Equal Opportunity Employer notice: Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. If you require a workplace accommodation during the application or hiring process, please visit the accommodations information page for more details. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Our compensation reflects cost of labor across several US geographic markets. Base pay ranges cited are for example purposes and may vary based on location, knowledge, skills, and experience. Amazon is a total compensation company and may offer equity, sign-on payments, and other benefits as part of a complete package. Company: Annapurna Labs (U.S.) Inc. Job ID: A3091748
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