Microchip
Senior Technical Staff Engineer - Design (IO Lead Design-FPGA)
Microchip, San Jose, California, United States, 95199
Overview
Are you looking for a unique opportunity to be part of something great? Join a 17,000-member team that works on the technology that powers the world around us. Microchip Technology Inc. offers an atmosphere of trust, empowerment, respect, diversity, and communication, with opportunities to own a piece of a multi-billion dollar global organization.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports growth and stability. We are challenged by an incredible array of products and solutions with unlimited career potential. Our leadership development programs support career growth, and we proudly enroll over a thousand people annually. We value employee development, values-based decision making, and a strong sense of community, guided by our Vision, Mission, and 11 Guiding Values."
Visit our careers page to see what exciting opportunities and company perks await.
Responsibilities
Provide technical leadership in architecture definition, design, modeling, integration, and verification of complex analog circuitry (clocking, Rx/Tx) integrated into the IOs of the FPGA.
Develop analog circuits for GPIO, HSIO, high-speed DDR, and other IO applications in advanced FinFET nodes.
Collaborate with the architecture team to understand chip requirements and translate them into circuit architectures; implement and simulate them.
Contribute to micro-architecture and circuit design, simulation, and optimization of IO blocks (clocking: PI, DLL, PLL; CTLE; VGA; Tx).
Collaborate with layout and ASIC PnR teams to optimize IO floorplan, placement, and routing of power and critical signals.
Develop IO system models to determine system budgets, identify performance bottlenecks, and create implementable design specs.
Drive analog and digital design AMS verification and layout across geographies and time zones.
Improve current and develop new calibration and training algorithms for IO sub-blocks to meet high-speed performance.
Work with the ESD engineer to integrate ESD design into IO blocks.
Provide layout guidance and mentorship of junior engineers.
Plan distribution of critical signals and clocks, placement of IO blocks, and design of the IO power distribution network.
Propose new mixed-signal flows for IO designs to enhance efficiency and quality of current and future designs.
Investigate new architectures and circuit design techniques for current and future generations of FPGA IOs.
Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up, and debugging.
Qualifications
Bachelors and/or Masters in Electrical Engineering, Physics, Computer Engineering, or Computer Science preferred.
15 years of proven silicon experience in design and verification of high-speed IOs and verification efforts across multiple technology nodes.
System modeling of IOs using MATLAB and SystemC / SystemVerilog.
Familiarity with FinFET technology and standard tools such as SPICE, Virtuoso AMS / Co-simulation, MATLAB.
Competency in HSPICE co-simulation and testbench generation and simulation.
Knowledge of high-speed design techniques (DDRx, PCIe, USB, MIPI) and calibrations.
Ability to write clean, readable presentations and demonstrate strong analytical, oral, and written communication skills.
Self-motivated, proactive team player with the ability to work to schedule requirements.
Travel: 0% – 25%
Details
Physical Attributes: Feeling, Handling, Hearing, Seeing, Talking; Works Alone; Works Around Others
Physical Requirements: 15% standing, 15% walking, 70% sitting; 100% indoors; Usual business hours
Employment Type: Full-Time
Experience: years
Vacancy: 1
Monthly Salary: 88000 - 232000
Benefits We offer a total compensation package that ranks among the best in the industry. It includes base pay, restricted stock units, and quarterly bonus. Our package also includes health benefits from day one, retirement savings plans, and an industry-leading ESPP with a 2-year look-back feature. Find more information about all our benefits at the link below.
The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000. Range depends on location, skills, and experience.
Microchip Technology Inc. is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
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People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports growth and stability. We are challenged by an incredible array of products and solutions with unlimited career potential. Our leadership development programs support career growth, and we proudly enroll over a thousand people annually. We value employee development, values-based decision making, and a strong sense of community, guided by our Vision, Mission, and 11 Guiding Values."
Visit our careers page to see what exciting opportunities and company perks await.
Responsibilities
Provide technical leadership in architecture definition, design, modeling, integration, and verification of complex analog circuitry (clocking, Rx/Tx) integrated into the IOs of the FPGA.
Develop analog circuits for GPIO, HSIO, high-speed DDR, and other IO applications in advanced FinFET nodes.
Collaborate with the architecture team to understand chip requirements and translate them into circuit architectures; implement and simulate them.
Contribute to micro-architecture and circuit design, simulation, and optimization of IO blocks (clocking: PI, DLL, PLL; CTLE; VGA; Tx).
Collaborate with layout and ASIC PnR teams to optimize IO floorplan, placement, and routing of power and critical signals.
Develop IO system models to determine system budgets, identify performance bottlenecks, and create implementable design specs.
Drive analog and digital design AMS verification and layout across geographies and time zones.
Improve current and develop new calibration and training algorithms for IO sub-blocks to meet high-speed performance.
Work with the ESD engineer to integrate ESD design into IO blocks.
Provide layout guidance and mentorship of junior engineers.
Plan distribution of critical signals and clocks, placement of IO blocks, and design of the IO power distribution network.
Propose new mixed-signal flows for IO designs to enhance efficiency and quality of current and future designs.
Investigate new architectures and circuit design techniques for current and future generations of FPGA IOs.
Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up, and debugging.
Qualifications
Bachelors and/or Masters in Electrical Engineering, Physics, Computer Engineering, or Computer Science preferred.
15 years of proven silicon experience in design and verification of high-speed IOs and verification efforts across multiple technology nodes.
System modeling of IOs using MATLAB and SystemC / SystemVerilog.
Familiarity with FinFET technology and standard tools such as SPICE, Virtuoso AMS / Co-simulation, MATLAB.
Competency in HSPICE co-simulation and testbench generation and simulation.
Knowledge of high-speed design techniques (DDRx, PCIe, USB, MIPI) and calibrations.
Ability to write clean, readable presentations and demonstrate strong analytical, oral, and written communication skills.
Self-motivated, proactive team player with the ability to work to schedule requirements.
Travel: 0% – 25%
Details
Physical Attributes: Feeling, Handling, Hearing, Seeing, Talking; Works Alone; Works Around Others
Physical Requirements: 15% standing, 15% walking, 70% sitting; 100% indoors; Usual business hours
Employment Type: Full-Time
Experience: years
Vacancy: 1
Monthly Salary: 88000 - 232000
Benefits We offer a total compensation package that ranks among the best in the industry. It includes base pay, restricted stock units, and quarterly bonus. Our package also includes health benefits from day one, retirement savings plans, and an industry-leading ESPP with a 2-year look-back feature. Find more information about all our benefits at the link below.
The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000. Range depends on location, skills, and experience.
Microchip Technology Inc. is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
#J-18808-Ljbffr