Fox Point Recruitment LLC
Senior Analog IC Design Engineer
Fox Point Recruitment LLC, Santa Clara, California, us, 95053
Overview
Job Title:
Senior Analog IC Design Engineer, Senior Staff (T4) Location:
Hybrid (2 days a week in the office) Responsibilities
Work with multi-functional teams to deliver high-speed Ethernet products. Define specifications based on link budget, behavioral modeling, and transistor-level feasibility. Drive schematic design and collaborate on mask design for implementation. Work with the team to drive designs into volume production and delight customers. Qualifications
Masters degree and/or PhD in Electrical Engineering and 3+ years of experience. The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers. Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques. Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization. Experience in the following areas is desirable: Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) Familiarity with CDR architectures and implementations Design experience in advanced CMOS technologies, design with FinFet technology Experience in lab testing of high-speed transceivers Modeling of passive on-chip elements such as inductor, T-coil, and transformer Able to build VerilogA/AMS behavioral models Able to analyze and lead characterization data from lab and volume testing Knowledge of ESD requirements Compensation
Expected Base Pay Range (USD):
The successful candidates starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefits
There will be a total compensation package with a base, bonus and equity. Health and financial wellbeing are part of the package and includes: Flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer.
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Job Title:
Senior Analog IC Design Engineer, Senior Staff (T4) Location:
Hybrid (2 days a week in the office) Responsibilities
Work with multi-functional teams to deliver high-speed Ethernet products. Define specifications based on link budget, behavioral modeling, and transistor-level feasibility. Drive schematic design and collaborate on mask design for implementation. Work with the team to drive designs into volume production and delight customers. Qualifications
Masters degree and/or PhD in Electrical Engineering and 3+ years of experience. The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers. Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques. Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization. Experience in the following areas is desirable: Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) Familiarity with CDR architectures and implementations Design experience in advanced CMOS technologies, design with FinFet technology Experience in lab testing of high-speed transceivers Modeling of passive on-chip elements such as inductor, T-coil, and transformer Able to build VerilogA/AMS behavioral models Able to analyze and lead characterization data from lab and volume testing Knowledge of ESD requirements Compensation
Expected Base Pay Range (USD):
The successful candidates starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefits
There will be a total compensation package with a base, bonus and equity. Health and financial wellbeing are part of the package and includes: Flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer.
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