Altera
Altera
.We are seeking a highly motivated & passionate for safety, Functional Safety Architect to join our semiconductor architecture design team. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanisms derived from safety analyses; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices. You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certification.**Key Responsibilities** Perform safety analyses (FTA, FMEA, DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.* Document and present defensible safety case evidences aligned with IEC 61508, ISO 26262 ensuring clarity and traceability for stakeholders and assessors.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$178.9k - $259.0k USD#LI-CG1Minimum RequirementsBS + 10 Years of silicon industry experience or MS + 8 years of silicon industry experienceExperience in certifying devices from concept through certification for ASICs/PLDs/CPUs with EXIDA, TUeV or EquivalentSkilled with SysML, FMEA/FMEDA, FTA, HAZOP and requirements-management tooling (e.g., Jama).Demonstrated strong ability to move seamlessly between levels of abstraction – from system to the “nuts and bolts” implementation Excellent written & oral communication skills to construct clear, evidence-based safety arguments and build trust in safety cases with both internal and external stakeholders**Preferred Qualifications:** Familiarity with RTL coding and simulations/debug of SoC Architectures.Ability to resolve complex issues in creative, efficient, and effective ways #J-18808-Ljbffr
.We are seeking a highly motivated & passionate for safety, Functional Safety Architect to join our semiconductor architecture design team. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanisms derived from safety analyses; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices. You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certification.**Key Responsibilities** Perform safety analyses (FTA, FMEA, DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.* Document and present defensible safety case evidences aligned with IEC 61508, ISO 26262 ensuring clarity and traceability for stakeholders and assessors.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$178.9k - $259.0k USD#LI-CG1Minimum RequirementsBS + 10 Years of silicon industry experience or MS + 8 years of silicon industry experienceExperience in certifying devices from concept through certification for ASICs/PLDs/CPUs with EXIDA, TUeV or EquivalentSkilled with SysML, FMEA/FMEDA, FTA, HAZOP and requirements-management tooling (e.g., Jama).Demonstrated strong ability to move seamlessly between levels of abstraction – from system to the “nuts and bolts” implementation Excellent written & oral communication skills to construct clear, evidence-based safety arguments and build trust in safety cases with both internal and external stakeholders**Preferred Qualifications:** Familiarity with RTL coding and simulations/debug of SoC Architectures.Ability to resolve complex issues in creative, efficient, and effective ways #J-18808-Ljbffr