Northrop Grumman
Digital Engineer/Principal Digital Engineer (FPGA Engineer) - R10207998
Northrop Grumman, Orlando, Florida, us, 32885
Overview
Northrop Grumman is seeking a Digital Engineer/Principal Digital Engineer (FPGA Engineer) in Orlando, FL to support the Cross-Domain Handling of Releasable Data (CHORD) portfolio. This FPGA Engineer role involves on-site work and may consider candidates for Level 2 (Digital Engineer) or Level 3 (Principal Digital Engineer).
Locations considered: Orlando, FL (on-site daily); other potential locations include Bellevue, NE; McLean, VA; or Huntsville, AL.
Roles & Responsibilities
Design and develop digital circuits and systems, including FPGAs.
Generate and update digital system requirements and select components based on analysis of specifications and reliability.
Use modeling and simulation tools to expedite firmware development and testing before hardware is available.
Develop test plans and implement rigorous testing and validation processes for digital designs to ensure functionality, performance and security requirements are met.
Adhere to coding standards, revision control practices, and peer review procedures.
Conduct tests using high-speed oscilloscopes, signal generators, signal analyzers, and FPGA debugging tools; analyze test data.
Significant involvement in field/on-site testing.
Collaborate within a development team to understand system-level interdependencies that impact circuit requirements and design constraints.
Basic Qualifications
Level 2 (Digital Engineer): Bachelor’s degree in a STEM field and 2 years of related technical experience; Master’s degree in a STEM field and 0 years of related technical experience.
Level 3 (Principal Digital Engineer): Bachelor’s degree in a STEM field with 5 years of related technical experience; Master’s degree with 3 years; PhD with 1 year of related technical experience.
Current DoD Secret Clearance.
Ability to translate system performance and operational specifications into hardware requirements, design, and test specifications.
Hands-on hardware/software integration experience of complex digital subsystems (e.g., FPGA-based circuits, embedded processors, high-speed interfaces).
Experience in FPGA design and development using VHDL or Verilog.
Experience with FPGA design verification using simulation, hardware verification, and debugging tools (e.g., ChipScope).
Experience integrating 3rd party Vendor IP cores with internal designs.
Experience with version control tools (e.g., Git).
Experience using lab equipment such as oscilloscopes and logic analyzers.
Preferred Qualifications
Experience with AMD/Xilinx products and toolsets (Vivado, Vivado IP Integrator, Modelsim/Questa, AMD/Xilinx Vitis IDE, Xilinx/AMD Vitis HLS).
Experience with high-speed FPGA PCIe interfaces and external networks.
Experience in creating and managing technical documentation (architecture and interface control documents).
Experience with board-level electrical design and debugging.
Primary Level Salary Range: $85,000.00 - $127,400.00
Secondary Level Salary Range: $104,800.00 - $157,200.00
The above salary ranges are general guidelines. Northrop Grumman considers various factors when determining base salary offers, including scope and responsibilities, candidate experience, education, skills, and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses may be awarded based on individual contributions and company results. Some roles may be eligible for Long Term Incentives for certain VP/Director positions. Northrop Grumman provides a variety of benefits including health insurance, life and disability insurance, a savings plan, company-paid holidays, and paid time off (PTO).
The application period for the job is estimated to be 20 days from the posting date, but this timeline may be shortened or extended depending on business needs and candidate availability.
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for government-cleared positions.
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Locations considered: Orlando, FL (on-site daily); other potential locations include Bellevue, NE; McLean, VA; or Huntsville, AL.
Roles & Responsibilities
Design and develop digital circuits and systems, including FPGAs.
Generate and update digital system requirements and select components based on analysis of specifications and reliability.
Use modeling and simulation tools to expedite firmware development and testing before hardware is available.
Develop test plans and implement rigorous testing and validation processes for digital designs to ensure functionality, performance and security requirements are met.
Adhere to coding standards, revision control practices, and peer review procedures.
Conduct tests using high-speed oscilloscopes, signal generators, signal analyzers, and FPGA debugging tools; analyze test data.
Significant involvement in field/on-site testing.
Collaborate within a development team to understand system-level interdependencies that impact circuit requirements and design constraints.
Basic Qualifications
Level 2 (Digital Engineer): Bachelor’s degree in a STEM field and 2 years of related technical experience; Master’s degree in a STEM field and 0 years of related technical experience.
Level 3 (Principal Digital Engineer): Bachelor’s degree in a STEM field with 5 years of related technical experience; Master’s degree with 3 years; PhD with 1 year of related technical experience.
Current DoD Secret Clearance.
Ability to translate system performance and operational specifications into hardware requirements, design, and test specifications.
Hands-on hardware/software integration experience of complex digital subsystems (e.g., FPGA-based circuits, embedded processors, high-speed interfaces).
Experience in FPGA design and development using VHDL or Verilog.
Experience with FPGA design verification using simulation, hardware verification, and debugging tools (e.g., ChipScope).
Experience integrating 3rd party Vendor IP cores with internal designs.
Experience with version control tools (e.g., Git).
Experience using lab equipment such as oscilloscopes and logic analyzers.
Preferred Qualifications
Experience with AMD/Xilinx products and toolsets (Vivado, Vivado IP Integrator, Modelsim/Questa, AMD/Xilinx Vitis IDE, Xilinx/AMD Vitis HLS).
Experience with high-speed FPGA PCIe interfaces and external networks.
Experience in creating and managing technical documentation (architecture and interface control documents).
Experience with board-level electrical design and debugging.
Primary Level Salary Range: $85,000.00 - $127,400.00
Secondary Level Salary Range: $104,800.00 - $157,200.00
The above salary ranges are general guidelines. Northrop Grumman considers various factors when determining base salary offers, including scope and responsibilities, candidate experience, education, skills, and current market conditions.
Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses may be awarded based on individual contributions and company results. Some roles may be eligible for Long Term Incentives for certain VP/Director positions. Northrop Grumman provides a variety of benefits including health insurance, life and disability insurance, a savings plan, company-paid holidays, and paid time off (PTO).
The application period for the job is estimated to be 20 days from the posting date, but this timeline may be shortened or extended depending on business needs and candidate availability.
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for government-cleared positions.
#J-18808-Ljbffr