Astera Labs is hiring: Senior Hardware Board Validation Engineer in San Jose

Senior Hardware Board Validation Engineer This range is provided by Astera Labs. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $150,000.00/yr - $195,000.00/yr Additional compensation types Annual Bonus and RSUs Overview As a Senior Electrical Validation Engineer at Astera Labs, you will join a dedicated Hardware Engineering team responsible for developing boards that incorporate Astera Labs\' range of connectivity products. These products are utilized by leading cloud service providers, server manufacturers, and network OEMs. Your primary responsibility will involve collaborating closely with EE and ASIC designers to develop and implement electrical validation plans for internal and external Astera Labs products. You will also support manufacturing activities and contribute to other company initiatives. Key Responsibilities Develop and execute electrical validation plans, jointly with EE Define testing methodologies Debug complex multi-point failures in circuits, and investigate and propose solutions Specify test equipment, develop test fixtures, help improve hardware lab functions Support various design and manufacturing initiatives Required Experience Strong technical background in electrical engineering and circuit analysis and debug. Bachelor degree in EE and 3 years of experience in test or design. Strong understanding of electronic circuits and test approach Ability to produce test description from the schematic design and execute + document results Working knowledge of schematics + layout tools (able to read designs) Experience with working on complex electronics products Experience with lab equipment (scopes, VNA, TDR, e-loads, environmental chambers) Scripting automation tasks with lab equipment Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Preferred Experience Experience with measurements of high-speed interfaces (PCIe, DDR, 25/50G/100G SERDES) Experience with EMI/EMC compliance PLM experience with Arena or equivalent Experience with ASIC/silicon development process Experience working with CMs (off-shore a plus) Seniority level Mid-Senior level Employment type Full-time Job function Product Management and Project Management Industries Semiconductor Manufacturing and Computer Hardware Manufacturing Get notified about new Validation Engineer jobs in San Jose, CA . #J-18808-Ljbffr