Intelliswift - An LTTS Company
Design Verification Engineer
Intelliswift - An LTTS Company, Sunnyvale, California, United States, 94087
Job Description
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry. Responsibilities
Define and implement IP/SoC verification plans Build verification test benches Drive Design Verification to closure Debug and resolve functional failures Collaborate with cross-functional teams Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification Track record of 'first-pass success' in ASIC development cycles 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Preferred Qualifications
Experience in development of UVM based verification environments from scratch Experience verifying GPU/CPU designs Experience with micro-architectural performance verification Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with verification of ARM/RISC-V based sub-systems or SoCs We are an equal opportunities employer and welcome applications from all qualified candidates.
#J-18808-Ljbffr
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry. Responsibilities
Define and implement IP/SoC verification plans Build verification test benches Drive Design Verification to closure Debug and resolve functional failures Collaborate with cross-functional teams Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification Track record of 'first-pass success' in ASIC development cycles 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Preferred Qualifications
Experience in development of UVM based verification environments from scratch Experience verifying GPU/CPU designs Experience with micro-architectural performance verification Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with verification of ARM/RISC-V based sub-systems or SoCs We are an equal opportunities employer and welcome applications from all qualified candidates.
#J-18808-Ljbffr