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SpanIdea Systems

PCIe Validation Lead

SpanIdea Systems, San Francisco, California, United States, 94199

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Make a Difference - Be Part of Our Team | Customer Success And Talent Acquisition Specialist at SpanIdea Systems

We are seeking a highly experienced engineer with deep expertise inPCIe Gen5/6 validationonHAPS platforms. This role will focus on bringing up and debugging next-generation PCIe Gen6/7for complex SoC designs. The engineer will work across emulation platforms, lead subsystem validation, and guide junior team members. Key Responsibilities Validate and debug PCIe Gen6/7 on HAPS and other emulation platforms (Zebu, Palladium, Protium, Veloce). Debug SoC failures, analyze netlists, and enable new features. Drive subsystem bring-up with cross-functional teams (design, BIOS, firmware). Mentor and support junior engineers in debugging and validation. Requirements Hands-on experience in SoC validation, emulation, or verification. Proven hands-on expertise in PCIe Gen5/6 bring-up and debug. Familiarity with memory subsystems (HBM/DDR) is required; knowledge of BIOS/Linux kernel is a plus. Seniority level: Mid-Senior level Employment type: Full-time Job function: Quality Assurance Industries: Software Development

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