Nokia
Overview
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The
Network Infrastructure
group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.
Join
Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Qualifications
Understanding of semiconductor processes and device physics
Semiconductor FAB / cleanroom environment experience
Understanding of statistical process control methods
Familiarity with or direct experience in most of the standard III-V process technologies required for wafer fabrication such as epitaxy, wet etching, plasma etching, metal deposition, and photolithography
Ability to work in a CAD design environment, generate and maintain mask files as well as die level test structure files
Database interrogation, statistical analysis skills, and design of experiments
Excellent communications skills and ability to present data, ideas, and recommendations to a diverse audience
Education Required:
B.S. with at least 3 years of work experience. M.S. level or higher in Electrical Engineering, Photonics, Physics, or Materials Science is preferred.
Responsibilities
Manage quality and yield of PIC wafers based on knowledge of fab processes, device physics, and the analysis of test and reliability data
Troubleshoot and resolve process deviations and test failures through a detailed analysis of test data and process history
Establish and maintain inline FAB process specifications
Continuous surveillance of inline FAB process capability (CPK)
Investigate the impact of design rules on process yields, develop test structures for effective process control
Initiate and carry out yield improvement activities, from inception through qualification and implementation
Support next-generation PIC platform development and participate in technology development, transfer, and ramp activities to meet yield, reliability, cost, and device performance goals
Support Process Engineering to improve process stability and capability
Support Operations to improve throughput and cycle time
#J-18808-Ljbffr
Network Infrastructure
group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.
Join
Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Qualifications
Understanding of semiconductor processes and device physics
Semiconductor FAB / cleanroom environment experience
Understanding of statistical process control methods
Familiarity with or direct experience in most of the standard III-V process technologies required for wafer fabrication such as epitaxy, wet etching, plasma etching, metal deposition, and photolithography
Ability to work in a CAD design environment, generate and maintain mask files as well as die level test structure files
Database interrogation, statistical analysis skills, and design of experiments
Excellent communications skills and ability to present data, ideas, and recommendations to a diverse audience
Education Required:
B.S. with at least 3 years of work experience. M.S. level or higher in Electrical Engineering, Photonics, Physics, or Materials Science is preferred.
Responsibilities
Manage quality and yield of PIC wafers based on knowledge of fab processes, device physics, and the analysis of test and reliability data
Troubleshoot and resolve process deviations and test failures through a detailed analysis of test data and process history
Establish and maintain inline FAB process specifications
Continuous surveillance of inline FAB process capability (CPK)
Investigate the impact of design rules on process yields, develop test structures for effective process control
Initiate and carry out yield improvement activities, from inception through qualification and implementation
Support next-generation PIC platform development and participate in technology development, transfer, and ramp activities to meet yield, reliability, cost, and device performance goals
Support Process Engineering to improve process stability and capability
Support Operations to improve throughput and cycle time
#J-18808-Ljbffr