Apple Inc.
Cupertino, California, United States
Description As an ASIC STA Engineer, you will be responsible for various aspects of SOC design, including:
Ownership of full chip and block-level timing closure throughout the project.
Developing and maintaining methodology and flows related to timing verification and closure.
Generating block and full chip timing constraints.
Working on Apple SoC (System-on-Chip) chips in deep sub-micron technologies for high-end mobile applications.
Collaborating with multi-functional teams to resolve complex timing issues in major SoC components.
Minimum Qualifications
Bachelor's Degree + 3 Years of Experience
Preferred Qualifications
Strong fundamentals in Digital design
Self-motivated and proactive
Proficient in scripting languages such as TCL and Perl
Familiarity with ASIC design timing concepts
Experience with STA tools like PrimeTime is a plus
Knowledge of front-end tools and methodologies, including Synthesis and Logic equivalence checks
Experience with constraint analysis and debugging using tools like Synopsys GCA is desirable
Understanding of timing corners/modes, process variations, and signal integrity issues is a plus
Effective communication skills across teams
Additional Information Apple offers a competitive total compensation package, including base pay within a range based on skills and experience, stock programs, benefits such as medical and dental coverage, retirement plans, discounts, educational reimbursement, and potential bonuses or relocation assistance. The base pay range for this role is $147,400 to $272,100.
Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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Description As an ASIC STA Engineer, you will be responsible for various aspects of SOC design, including:
Ownership of full chip and block-level timing closure throughout the project.
Developing and maintaining methodology and flows related to timing verification and closure.
Generating block and full chip timing constraints.
Working on Apple SoC (System-on-Chip) chips in deep sub-micron technologies for high-end mobile applications.
Collaborating with multi-functional teams to resolve complex timing issues in major SoC components.
Minimum Qualifications
Bachelor's Degree + 3 Years of Experience
Preferred Qualifications
Strong fundamentals in Digital design
Self-motivated and proactive
Proficient in scripting languages such as TCL and Perl
Familiarity with ASIC design timing concepts
Experience with STA tools like PrimeTime is a plus
Knowledge of front-end tools and methodologies, including Synthesis and Logic equivalence checks
Experience with constraint analysis and debugging using tools like Synopsys GCA is desirable
Understanding of timing corners/modes, process variations, and signal integrity issues is a plus
Effective communication skills across teams
Additional Information Apple offers a competitive total compensation package, including base pay within a range based on skills and experience, stock programs, benefits such as medical and dental coverage, retirement plans, discounts, educational reimbursement, and potential bonuses or relocation assistance. The base pay range for this role is $147,400 to $272,100.
Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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