Apple
Mixed-Signal Clocking and Control RTL Design Engineer
Apple, Cupertino, California, United States, 95014
Mixed-Signal Clocking and Control RTL Design Engineer
Cupertino, California, United States
Summary
At Apple, we are dedicated to designing products that enrich the lives of our users. Are you passionate about tackling challenges that have yet to be resolved? Do you thrive in innovative environments? We have a technically demanding Mixed-Signal Clocking and Control RTL Design position on our team. Description
In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs. Minimum Qualifications
MS degree in technical discipline with minimum of 3 years of relevant experience. Preferred Qualifications
Excellent knowledge of digital logic gates, clocking and state elements Excellent knowledge of writing synthesizable code in SystemVerilog Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators Prior experience working on clocking circuits such as PLLs/DLLs/CDRs Familiarity with DACs and oversampling modulators Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling Familiarity with the basics of digital signal processing and closed loop control Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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At Apple, we are dedicated to designing products that enrich the lives of our users. Are you passionate about tackling challenges that have yet to be resolved? Do you thrive in innovative environments? We have a technically demanding Mixed-Signal Clocking and Control RTL Design position on our team. Description
In this role, you will be responsible for designing logic used to calibrate and control circuits such as oscillators, delay lines and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal processing and control systems. You will need to analyze control loops for critical parameters such as gain, latency, transients and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs. Minimum Qualifications
MS degree in technical discipline with minimum of 3 years of relevant experience. Preferred Qualifications
Excellent knowledge of digital logic gates, clocking and state elements Excellent knowledge of writing synthesizable code in SystemVerilog Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators Prior experience working on clocking circuits such as PLLs/DLLs/CDRs Familiarity with DACs and oversampling modulators Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling Familiarity with the basics of digital signal processing and closed loop control Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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