Qualcomm
Company: Qualcomm Technologies, Inc.
Job Area: Engineering Group, Engineering Group > CPU Engineering
General Summary
NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. About The Role
In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. Key Responsibilities
STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Strong experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Preferred Qualification/Skills
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Expert in scripting languages – TCL, Perl, Python Basic knowledge of device physics This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
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NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. About The Role
In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. Key Responsibilities
STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Strong experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Preferred Qualification/Skills
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Expert in scripting languages – TCL, Perl, Python Basic knowledge of device physics This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
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