NVIDIA
Senior ASIC Physical Design Engineer, Netlisting
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Senior ASIC Physical Design Engineer, Netlisting
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NVIDIA What You'll Be Doing
You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation. What We Need To See
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience. Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools. Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools. Background with logic synthesis at either block or full-chip level, at project execution and/or flow development. Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Expertise and in-depth knowledge of industry standard EDA tools in related fields. Proficiency in programming and scripting languages, such as Perl, TCL, Make, Python, etc. Ways To Stand Out From The Crowd
Experience in logic synthesis and equivalence checking/FV. Familiarity with industry tools and flow. Strong hands-on debugging capability and problem-solving skills. Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc. Candidates who demonstrate experience or a strong drive to improve workflows and productivity through effective AI utilization will stand out. Compensation and Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Application Details
Applications for this job will be accepted at least until October 10, 2025. Equal Opportunity
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. JR2005474 Austin, TX
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Join to apply for the
Senior ASIC Physical Design Engineer, Netlisting
role at
NVIDIA What You'll Be Doing
You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation. What We Need To See
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience. Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools. Deep understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools. Background with logic synthesis at either block or full-chip level, at project execution and/or flow development. Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Expertise and in-depth knowledge of industry standard EDA tools in related fields. Proficiency in programming and scripting languages, such as Perl, TCL, Make, Python, etc. Ways To Stand Out From The Crowd
Experience in logic synthesis and equivalence checking/FV. Familiarity with industry tools and flow. Strong hands-on debugging capability and problem-solving skills. Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc. Candidates who demonstrate experience or a strong drive to improve workflows and productivity through effective AI utilization will stand out. Compensation and Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Application Details
Applications for this job will be accepted at least until October 10, 2025. Equal Opportunity
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. JR2005474 Austin, TX
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