Eximietas Design
RTL Design Engineer – UCIe / Chiplet Interconnect
Eximietas Design, San Jose, California, United States, 95199
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Overview
We are seeking a highly experienced
RTL Design Engineer
with
10+ years of RTL design expertise
and
hands-on UCIe controller implementation experience
to join our SoC architecture team. In this role, you will own the
RTL design and micro-architecture for UCIe controllers
(adapter and link layer), enabling high-performance die-to-die interconnects for next-generation multi-die SoCs. You will work closely with system architects, verification teams, and physical design engineers to deliver high-bandwidth, low-power chiplet interconnect solutions. Responsibilities
Own RTL design and micro-architecture for UCIe controller (adapter/link layer logic, register interface, flow control, error handling). Define block-level micro-architecture specifications and maintain design documentation. Ensure UCIe controller design meets PPA (power, performance, area) targets. Collaborate with PHY and SoC architects to ensure seamless die-to-die integration. Support verification teams with test plans, coverage closure, and debug. Drive synthesis, STA, lint, CDC/RDC sign-off, and DFT insertion for UCIe controller blocks. Participate in post-silicon bring-up and interoperability testing. Qualifications
Must-Have: 10+ years of hands-on RTL design experience using Verilog/SystemVerilog with multiple silicon tapeouts. Strong knowledge of UCIe specification (v1.x / v2.0), flow control, and error recovery. Background in high-speed interface protocols (PCIe, CXL, AXI) and clock/power domain crossing techniques. Expertise with industry-standard EDA tools (simulation, synthesis, STA, lint, CDC). Track record of delivering production-quality RTL with timing and power closure. Preferred Qualifications
Experience with chiplet-based SoC architectures and multi-die package design flows. Familiarity with PHY/MAC interface design, signal integrity, and interoperability testing. Experience with formal verification, emulation, or FPGA prototyping. Excellent documentation and cross-functional communication skills. Why Join Us
Work on cutting-edge UCIe-based chiplet interconnect technology defining the future of multi-die SoCs. Collaborate with a world-class semiconductor engineering team. Competitive compensation, comprehensive benefits, and opportunities to influence product architecture. How to Apply
Apply or refer @ mohini.tyagi@eximietas.design Location: San Jose, CA
#J-18808-Ljbffr
We are seeking a highly experienced
RTL Design Engineer
with
10+ years of RTL design expertise
and
hands-on UCIe controller implementation experience
to join our SoC architecture team. In this role, you will own the
RTL design and micro-architecture for UCIe controllers
(adapter and link layer), enabling high-performance die-to-die interconnects for next-generation multi-die SoCs. You will work closely with system architects, verification teams, and physical design engineers to deliver high-bandwidth, low-power chiplet interconnect solutions. Responsibilities
Own RTL design and micro-architecture for UCIe controller (adapter/link layer logic, register interface, flow control, error handling). Define block-level micro-architecture specifications and maintain design documentation. Ensure UCIe controller design meets PPA (power, performance, area) targets. Collaborate with PHY and SoC architects to ensure seamless die-to-die integration. Support verification teams with test plans, coverage closure, and debug. Drive synthesis, STA, lint, CDC/RDC sign-off, and DFT insertion for UCIe controller blocks. Participate in post-silicon bring-up and interoperability testing. Qualifications
Must-Have: 10+ years of hands-on RTL design experience using Verilog/SystemVerilog with multiple silicon tapeouts. Strong knowledge of UCIe specification (v1.x / v2.0), flow control, and error recovery. Background in high-speed interface protocols (PCIe, CXL, AXI) and clock/power domain crossing techniques. Expertise with industry-standard EDA tools (simulation, synthesis, STA, lint, CDC). Track record of delivering production-quality RTL with timing and power closure. Preferred Qualifications
Experience with chiplet-based SoC architectures and multi-die package design flows. Familiarity with PHY/MAC interface design, signal integrity, and interoperability testing. Experience with formal verification, emulation, or FPGA prototyping. Excellent documentation and cross-functional communication skills. Why Join Us
Work on cutting-edge UCIe-based chiplet interconnect technology defining the future of multi-die SoCs. Collaborate with a world-class semiconductor engineering team. Competitive compensation, comprehensive benefits, and opportunities to influence product architecture. How to Apply
Apply or refer @ mohini.tyagi@eximietas.design Location: San Jose, CA
#J-18808-Ljbffr