Collabera
Field-Programmable Gate Arrays Engineer
Collabera, Sunnyvale, California, United States, 94087
This range is provided by Collabera. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$65.00/hr - $70.00/hr Core Responsibilities: Design, develop, and integrate FPGA logic and digital IP for high- and low-speed interfaces (I2C, SPI, PDM, PCIe, SerDes, GMSL, MIPI, DSI, CSI). Write, synthesize, and simulate RTL code (VHDL/Verilog) targeting Lattice FPGAs. Perform timing analysis, validation, and debug of RTL designs using test benches and simulation tools. Conduct lab-based validation and hardware bring-up using evaluation boards; program and test FPGA designs to verify performance. Collaborate closely with hardware, software, and vendor teams to align on design specifications and milestones. Deliver new FPGA code, validate outputs, and troubleshoot timing or signal integrity issues. Document design progress, validation results, and ensure deliverables meet project deadlines. Communicate effectively across teams, presenting technical findings and design updates. Maintain a consistent onsite presence to support integration and physical evaluation work. Must-Have Experience: 5+ years of FPGA development experience with hands-on RTL design and debug. Strong experience with VHDL and/or Verilog for FPGA logic development. Proficiency with Lattice toolchains (Lattice Diamond preferred) for synthesis, simulation, and programming. Deep understanding of digital interfaces and protocols, including: I2C, SPI, PDM, PCIe, SerDes, GMSL, MIPI, DSI, CSI. Strong background in FPGA synthesis, timing analysis, and constraint management. Experience building and using test benches for RTL validation and simulation. Familiarity with hardware bring-up, signal verification, and board-level testing using evaluation boards. Understanding of high-speed digital design concepts (latency, clock domain crossing, signal integrity). Prior experience in consumer electronics, semiconductor, or embedded hardware environments. Excellent communication, documentation, and presentation skills — ability to explain design work clearly to cross-functional teams. Comfortable working in a collaborative, lab-based environment with tight deadlines. Benefits:
The Company offers the following benefits for this position, subject to applicable eligibility requirements: medical insurance, dental insurance, vision insurance, 401(k) retirement plan, life insurance, long-term disability insurance, short-term disability insurance, paid parking/public transportation, (paid time, paid sick and safe time, hours of paid vacation time, weeks of paid parental leave, paid holidays annually - AS Applicable) Seniority level
Mid-Senior level Employment type
Contract Job function
Information Technology
#J-18808-Ljbffr
$65.00/hr - $70.00/hr Core Responsibilities: Design, develop, and integrate FPGA logic and digital IP for high- and low-speed interfaces (I2C, SPI, PDM, PCIe, SerDes, GMSL, MIPI, DSI, CSI). Write, synthesize, and simulate RTL code (VHDL/Verilog) targeting Lattice FPGAs. Perform timing analysis, validation, and debug of RTL designs using test benches and simulation tools. Conduct lab-based validation and hardware bring-up using evaluation boards; program and test FPGA designs to verify performance. Collaborate closely with hardware, software, and vendor teams to align on design specifications and milestones. Deliver new FPGA code, validate outputs, and troubleshoot timing or signal integrity issues. Document design progress, validation results, and ensure deliverables meet project deadlines. Communicate effectively across teams, presenting technical findings and design updates. Maintain a consistent onsite presence to support integration and physical evaluation work. Must-Have Experience: 5+ years of FPGA development experience with hands-on RTL design and debug. Strong experience with VHDL and/or Verilog for FPGA logic development. Proficiency with Lattice toolchains (Lattice Diamond preferred) for synthesis, simulation, and programming. Deep understanding of digital interfaces and protocols, including: I2C, SPI, PDM, PCIe, SerDes, GMSL, MIPI, DSI, CSI. Strong background in FPGA synthesis, timing analysis, and constraint management. Experience building and using test benches for RTL validation and simulation. Familiarity with hardware bring-up, signal verification, and board-level testing using evaluation boards. Understanding of high-speed digital design concepts (latency, clock domain crossing, signal integrity). Prior experience in consumer electronics, semiconductor, or embedded hardware environments. Excellent communication, documentation, and presentation skills — ability to explain design work clearly to cross-functional teams. Comfortable working in a collaborative, lab-based environment with tight deadlines. Benefits:
The Company offers the following benefits for this position, subject to applicable eligibility requirements: medical insurance, dental insurance, vision insurance, 401(k) retirement plan, life insurance, long-term disability insurance, short-term disability insurance, paid parking/public transportation, (paid time, paid sick and safe time, hours of paid vacation time, weeks of paid parental leave, paid holidays annually - AS Applicable) Seniority level
Mid-Senior level Employment type
Contract Job function
Information Technology
#J-18808-Ljbffr