Amazon
Overview
SOC Design - STA, Hardware Compute Group at Amazon. The team that built the Silicon IP AZ1 Neural Edge powering the latest Echo devices is seeking a Senior SoC Design-STA Engineer to continue innovating on behalf of customers. We are part of Amazon Lab126, known for Kindle, Echo, and Alexa, and we want you to help build on the success of our first generation ML accelerator at the edge. Responsibilities
Definition and development of signoff methodology and corresponding implementation solutions. Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. Streamlining timing signoff criteria, timing analysis methodologies and flows. Analyze and incorporate advanced timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. Collaborate with Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address timing sign-off challenges. Concepts of CRPR, clock paths analysis and tweaks to meet timing. Multi-Corner and Multi-Mode analysis and close timing at signoff corners across modes and delay corners for cells and interconnects. Basic Qualifications
Bachelor’s degree or equivalent in EE, CE, or CS. 7+ years of practical semiconductor implementation experience. Scripting experience with Perl, Python, Tcl, and shell; ability to automate flows. Proficiency with chip front-end and back-end tools such as Fusion Compiler, Design Compiler, ICC2 or Innovus, Primetime, Tempus. Preferred Qualifications
Master's or PhD in Computer Science, Electrical Engineering, or related field. Experience with memory compiler. Experience with formal equivalence – Cadence Conformal/Synopsys Formality. In-depth knowledge of the entire design process from design specification to architecture, RTL design and functional verification. Experience with DFT and DFM flows. Strong communication and analytical skills. Ability to work closely with IP Design teams and Backend Physical Design teams across multiple sites. Company and Equal Opportunity
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you require a workplace accommodation during the application and hiring process, please visit the Amazon accommodations page for more information. Job Details: Location: Camas, WA and surrounding areas; Employment type: Full-time; Seniority level: Not Applicable; Industry/Function: Manufacturing and Engineering; Job function: Software Development.
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SOC Design - STA, Hardware Compute Group at Amazon. The team that built the Silicon IP AZ1 Neural Edge powering the latest Echo devices is seeking a Senior SoC Design-STA Engineer to continue innovating on behalf of customers. We are part of Amazon Lab126, known for Kindle, Echo, and Alexa, and we want you to help build on the success of our first generation ML accelerator at the edge. Responsibilities
Definition and development of signoff methodology and corresponding implementation solutions. Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. Streamlining timing signoff criteria, timing analysis methodologies and flows. Analyze and incorporate advanced timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. Collaborate with Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address timing sign-off challenges. Concepts of CRPR, clock paths analysis and tweaks to meet timing. Multi-Corner and Multi-Mode analysis and close timing at signoff corners across modes and delay corners for cells and interconnects. Basic Qualifications
Bachelor’s degree or equivalent in EE, CE, or CS. 7+ years of practical semiconductor implementation experience. Scripting experience with Perl, Python, Tcl, and shell; ability to automate flows. Proficiency with chip front-end and back-end tools such as Fusion Compiler, Design Compiler, ICC2 or Innovus, Primetime, Tempus. Preferred Qualifications
Master's or PhD in Computer Science, Electrical Engineering, or related field. Experience with memory compiler. Experience with formal equivalence – Cadence Conformal/Synopsys Formality. In-depth knowledge of the entire design process from design specification to architecture, RTL design and functional verification. Experience with DFT and DFM flows. Strong communication and analytical skills. Ability to work closely with IP Design teams and Backend Physical Design teams across multiple sites. Company and Equal Opportunity
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you require a workplace accommodation during the application and hiring process, please visit the Amazon accommodations page for more information. Job Details: Location: Camas, WA and surrounding areas; Employment type: Full-time; Seniority level: Not Applicable; Industry/Function: Manufacturing and Engineering; Job function: Software Development.
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