nEye.ai
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IC Engineer - CMOS Design
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nEye.ai Join to apply for the
IC Engineer - CMOS Design
role at
nEye.ai This range is provided by nEye.ai. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$125,000.00/yr - $225,000.00/yr About Us:
nEye Systems, a well-funded optical switch startup founded in 2020, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability.
Job Overview:
As an IC Engineer - CMOS Design at nEye, you will have primary responsibility for the development and design of the custom CMOS integrated circuit that is part of the company’s SuperSwitch. This role will span the full ASIC development lifecycle, including architecture definition, design and verification, coordination with external CMOS design houses and fabrication foundries, and oversight of chip testing and validation. In addition to directing the test of the CMOS chip, you will be engaged with nEye Team Members in the strategic design, development, and implementation of all test procedures and systems to ensure the quality and performance of our SuperSwitch. This role involves both technical execution and leadership responsibilities. You will work closely with nEye Si Photonics designers, System and Software Engineers, Packaging Engineers and MEMS/Process Engineers to design and implement testing protocols, troubleshoot issues, and contribute to the advancement of our photonics products.
Key Responsibilities
Design and develop custom CMOS ASICs (analog, digital, or mixed-signal), from initial architecture through tape-out Collaborate with external CMOS design houses for schematic capture, layout, and physical verification (DRC/LVS) Engage with CMOS fabrication foundries to manage tape-out, mask generation, and production schedules Define and oversee test strategies for wafer- and package-level testing, including test fixture design and parametric test plans Analyze test results, identify performance issues, and implement design improvements or yield enhancements Ensure full documentation of design specifications, verification plans, and test reports Maintain project timelines, deliverables, and quality standards through close coordination with internal stakeholders and external vendors Stay current with industry advancements and best practices in CMOS process nodes, EDA tools, and test methodologies
Minimum Qualifications:
Master's or Ph.D. in Electrical Engineering, Mechanical Engineering, Photonics, Optics, or a related field 5+ years of experience in CMOS ASIC design, preferably in analog, digital, or mixed-signal environments Demonstrated proficiency with EDA tools (Cadence, Synopsys, Mentor, etc.) for design, simulation, and layout Experience working directly with fabless semiconductor models, including coordination with design houses and foundries Familiarity with DFT (Design for Test) and ATE (Automatic Test Equipment) environments Fundamental understanding of CMOS fabrication processes, process variations, and reliability considerations Excellent analytical and problem-solving skills
Preferred Skills:
Experience with the design and fabrication of MEMS structures and optoelectronic devices Understanding of industry standards for photonics testing Familiarity with package design and interactions between IC design and package layout Ability to interpret and negotiate foundry PDKs and design rule documentation Experience in design and fabrication of devices with both micro- and nano-scale features
Benefits & Perks:
Competitive salary and equity package, including early-stage company stock options 401k plan Full healthcare coverage: medical, dental, and vision Fitness center access
nEye is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.
Starting salary will depend on relevant experience, skills, training, education, market demands, and the ultimate job duties and requirements. Seniority level
Seniority level Not Applicable Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at nEye.ai by 2x Get notified about new Design Engineer jobs in
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Mechanical Design Engineer, Cabin Systems
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IC Engineer - CMOS Design
role at
nEye.ai Join to apply for the
IC Engineer - CMOS Design
role at
nEye.ai This range is provided by nEye.ai. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$125,000.00/yr - $225,000.00/yr About Us:
nEye Systems, a well-funded optical switch startup founded in 2020, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability.
Job Overview:
As an IC Engineer - CMOS Design at nEye, you will have primary responsibility for the development and design of the custom CMOS integrated circuit that is part of the company’s SuperSwitch. This role will span the full ASIC development lifecycle, including architecture definition, design and verification, coordination with external CMOS design houses and fabrication foundries, and oversight of chip testing and validation. In addition to directing the test of the CMOS chip, you will be engaged with nEye Team Members in the strategic design, development, and implementation of all test procedures and systems to ensure the quality and performance of our SuperSwitch. This role involves both technical execution and leadership responsibilities. You will work closely with nEye Si Photonics designers, System and Software Engineers, Packaging Engineers and MEMS/Process Engineers to design and implement testing protocols, troubleshoot issues, and contribute to the advancement of our photonics products.
Key Responsibilities
Design and develop custom CMOS ASICs (analog, digital, or mixed-signal), from initial architecture through tape-out Collaborate with external CMOS design houses for schematic capture, layout, and physical verification (DRC/LVS) Engage with CMOS fabrication foundries to manage tape-out, mask generation, and production schedules Define and oversee test strategies for wafer- and package-level testing, including test fixture design and parametric test plans Analyze test results, identify performance issues, and implement design improvements or yield enhancements Ensure full documentation of design specifications, verification plans, and test reports Maintain project timelines, deliverables, and quality standards through close coordination with internal stakeholders and external vendors Stay current with industry advancements and best practices in CMOS process nodes, EDA tools, and test methodologies
Minimum Qualifications:
Master's or Ph.D. in Electrical Engineering, Mechanical Engineering, Photonics, Optics, or a related field 5+ years of experience in CMOS ASIC design, preferably in analog, digital, or mixed-signal environments Demonstrated proficiency with EDA tools (Cadence, Synopsys, Mentor, etc.) for design, simulation, and layout Experience working directly with fabless semiconductor models, including coordination with design houses and foundries Familiarity with DFT (Design for Test) and ATE (Automatic Test Equipment) environments Fundamental understanding of CMOS fabrication processes, process variations, and reliability considerations Excellent analytical and problem-solving skills
Preferred Skills:
Experience with the design and fabrication of MEMS structures and optoelectronic devices Understanding of industry standards for photonics testing Familiarity with package design and interactions between IC design and package layout Ability to interpret and negotiate foundry PDKs and design rule documentation Experience in design and fabrication of devices with both micro- and nano-scale features
Benefits & Perks:
Competitive salary and equity package, including early-stage company stock options 401k plan Full healthcare coverage: medical, dental, and vision Fitness center access
nEye is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.
Starting salary will depend on relevant experience, skills, training, education, market demands, and the ultimate job duties and requirements. Seniority level
Seniority level Not Applicable Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at nEye.ai by 2x Get notified about new Design Engineer jobs in
Santa Clara, CA . Mountain View, CA $94,050.00-$141,550.00 2 weeks ago Sunnyvale, CA $139,000.00-$200,000.00 3 weeks ago Fremont, CA $139,000.00-$200,000.00 2 weeks ago Sunnyvale, CA $170,000.00-$240,000.00 3 weeks ago Menlo Park, CA $170,000.00-$240,000.00 19 hours ago Sunnyvale, CA $111,000.00-$164,000.00 19 hours ago Mechanical Product Design Engineer, Platforms, University Graduate
Sunnyvale, CA $105,000.00-$151,000.00 1 day ago Product Design Mechanical Engineer, Reality Labs
Sunnyvale, CA $204,000.00-$281,000.00 1 week ago Mechanical Manufacturing Engineer, Data Centers
Sunnyvale, CA $96,000.00-$138,000.00 21 hours ago Mechanical Design Engineer, Robotics Plastic, Optimus
Santa Clara, CA $120,000.00-$180,000.00 1 month ago Fremont, CA $70,000.00-$155,000.00 2 weeks ago Sunnyvale, CA $108,100.00-$182,900.00 1 week ago Mountain View, CA $181,000.00-$297,000.00 2 weeks ago San Jose, CA $120,000.00-$250,000.00 1 month ago Sunnyvale, CA $139,000.00-$200,000.00 2 weeks ago Pleasanton, CA $85,000.00-$135,000.00 1 month ago Mechanical Engineering Internship, Prototyping
Mechanical Design Engineer, Cabin Systems
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr