Silvus Technologies
Principal FPGA / RTL Design Engineer - Signal Processing
Silvus Technologies, Los Angeles, California, United States, 90079
Overview
Principal FPGA / RTL Design Engineer - Signal Processing role at Silvus Technologies. Based at Silvus headquarters in West Los Angeles, CA, with a hybrid schedule. Requires a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays). Responsibilities
Work with system engineers and digital design architects for wireless communication projects, including fixed-point design of signal processing blocks. RTL coding, simulation, and test bench development. FPGA synthesis and timing closure. Hardware verification and troubleshooting; familiarity with logic analyzers. Provide support to RF and Software Engineering Teams. Qualifications
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields. Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields. Demonstrated experience with fixed-point binary arithmetic and digital signal processing (DSP) designs. Deep knowledge of RTL design fundamentals using Verilog and SystemVerilog. Proven expertise with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs. Experience with Xilinx FPGAs, SoCs, and the Vivado IDE. Must be a U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts. All employment is contingent upon successful clearance of a background check. Preferred Knowledge, Skills, and Abilities
MS or PhD degree in Electrical Engineering, Computer Science, or relevant fields. Basic MATLAB skills. Scripting languages such as Perl and Python. Strong communication and presentation skills. Experience with wireless communication systems on FPGA or ASIC designs. Working Conditions
Office environment. Occasional exposure to heat, cold, and allergens during tests or field demonstrations. Physical requirements include lifting up to 20 lbs, bending, reaching, kneeling or squatting, and walking/moving in labs. Compensation
The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate’s experience and qualifications. CA Pay Range: $165,000 - $250,000 USD Note: As a U.S. Federal Contractor, all candidates for employment must be a U.S. Person (permanent resident or citizen). Stricter U.S. Citizen ONLY requirements may apply for some roles. All employment is contingent upon successful background check. Equal Employment Opportunity
Silvus is an equal-opportunity employer. We do not discrimination on the basis of race, color, age, religion or belief, ancestry, national origin, sex (including pregnancy), sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, physical or mental disability, protected veteran status, genetic information, political affiliation, or any other factor protected by applicable laws. Reasonable accommodations are available for applicants with disabilities. Contact us to request accommodation. Other
Silvus does not accept unsolicited resumes from individual recruiters or third-party agencies. No fee will be paid to third parties submitting unsolicited candidates.
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Principal FPGA / RTL Design Engineer - Signal Processing role at Silvus Technologies. Based at Silvus headquarters in West Los Angeles, CA, with a hybrid schedule. Requires a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays). Responsibilities
Work with system engineers and digital design architects for wireless communication projects, including fixed-point design of signal processing blocks. RTL coding, simulation, and test bench development. FPGA synthesis and timing closure. Hardware verification and troubleshooting; familiarity with logic analyzers. Provide support to RF and Software Engineering Teams. Qualifications
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields. Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields. Demonstrated experience with fixed-point binary arithmetic and digital signal processing (DSP) designs. Deep knowledge of RTL design fundamentals using Verilog and SystemVerilog. Proven expertise with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs. Experience with Xilinx FPGAs, SoCs, and the Vivado IDE. Must be a U.S. Person (U.S. Citizen, or Permanent Resident) due to clients under U.S. federal contracts. All employment is contingent upon successful clearance of a background check. Preferred Knowledge, Skills, and Abilities
MS or PhD degree in Electrical Engineering, Computer Science, or relevant fields. Basic MATLAB skills. Scripting languages such as Perl and Python. Strong communication and presentation skills. Experience with wireless communication systems on FPGA or ASIC designs. Working Conditions
Office environment. Occasional exposure to heat, cold, and allergens during tests or field demonstrations. Physical requirements include lifting up to 20 lbs, bending, reaching, kneeling or squatting, and walking/moving in labs. Compensation
The pay range is NOT a guarantee. It is based on market research and peer data, and will vary depending on the candidate’s experience and qualifications. CA Pay Range: $165,000 - $250,000 USD Note: As a U.S. Federal Contractor, all candidates for employment must be a U.S. Person (permanent resident or citizen). Stricter U.S. Citizen ONLY requirements may apply for some roles. All employment is contingent upon successful background check. Equal Employment Opportunity
Silvus is an equal-opportunity employer. We do not discrimination on the basis of race, color, age, religion or belief, ancestry, national origin, sex (including pregnancy), sexual orientation, gender identity and/or expression, marital, civil union or domestic partnership status, physical or mental disability, protected veteran status, genetic information, political affiliation, or any other factor protected by applicable laws. Reasonable accommodations are available for applicants with disabilities. Contact us to request accommodation. Other
Silvus does not accept unsolicited resumes from individual recruiters or third-party agencies. No fee will be paid to third parties submitting unsolicited candidates.
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