Mulya Technologies
Overview
Senior SerDes Architect and Lead — Hybrid We are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure and advanced wireless communications such as 5G networks and optical communications, automotive networking, LiDAR, radar systems, SatComm, Software Defined Radio (SDR) and other broadband communications. Responsibilities
Serve as a development lead for PAM4 ADC and DAC based wireline technologies, working with customers to understand requirements. Lead the development of high-performance transistor-level designs from initial specification through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications
10-20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed PAM4 architectures and topologies Experience designing high-performance building blocks (bandgap reference, op-amps, comparators, oscillators, DLLs, PLLs, CTLEs, CDRs, etc.) Understanding of equalization techniques (analog and digital) Track record of taking designs to production Ability to work with customers to define products that address needs Experience evaluating silicon on bench and familiarity with standard lab equipment Strong analytical understanding of transistor-level circuit design including noise and mismatch Experience with analog/digital behavioral modeling and/or synthesis of digital control blocks Familiarity with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE MATLAB understanding preferred but not mandatory Familiarity with electromigration and ESD compliance in submicron CMOS processes Familiarity with layout parasitic extraction tools and layout-dependent impairments in advanced CMOS Ability to work independently, create and adhere to schedules Strong written and verbal communication skills with teams across geographic locations Willingness to seek help and share knowledge proactively Contact
"Mining The Knowledge Community" Location
Austin, TX Salary
Not disclosed in this listing
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Senior SerDes Architect and Lead — Hybrid We are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure and advanced wireless communications such as 5G networks and optical communications, automotive networking, LiDAR, radar systems, SatComm, Software Defined Radio (SDR) and other broadband communications. Responsibilities
Serve as a development lead for PAM4 ADC and DAC based wireline technologies, working with customers to understand requirements. Lead the development of high-performance transistor-level designs from initial specification through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications
10-20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed PAM4 architectures and topologies Experience designing high-performance building blocks (bandgap reference, op-amps, comparators, oscillators, DLLs, PLLs, CTLEs, CDRs, etc.) Understanding of equalization techniques (analog and digital) Track record of taking designs to production Ability to work with customers to define products that address needs Experience evaluating silicon on bench and familiarity with standard lab equipment Strong analytical understanding of transistor-level circuit design including noise and mismatch Experience with analog/digital behavioral modeling and/or synthesis of digital control blocks Familiarity with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE MATLAB understanding preferred but not mandatory Familiarity with electromigration and ESD compliance in submicron CMOS processes Familiarity with layout parasitic extraction tools and layout-dependent impairments in advanced CMOS Ability to work independently, create and adhere to schedules Strong written and verbal communication skills with teams across geographic locations Willingness to seek help and share knowledge proactively Contact
"Mining The Knowledge Community" Location
Austin, TX Salary
Not disclosed in this listing
#J-18808-Ljbffr