SproutsAI
Actively hiring
Job type :
Full-time
Department :
Workplace type :
On-site
Experience :
15 - 18 years
About Us
We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here. About the Role
We are seeking for an experienced CPU Cache Sub-system Micro architect. Responsible for delivery of micro-architecture specifications of cutting-edge high performance, highly scalable multi-core, multi-thread, power-efficient CPU Cache sub-system. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area. Key Responsibilities
Define, own, and deliver detailed micro-architecture specifications for coherent cache sub-system Implement Product and Architecture requirements Define and analyze performance modeling studies for cache subsystem design choices Feasibility studies for Micro-architecture to RTL implementation Hands-on RTL design for critical functional blocks Hands-on experience with synthesis tools for micro-architecture trade-off analysis As part of highly configurable CPU IP, configure Features Development, assessment, and refinement of parameterizable RTL design to target power, performance, area, and timing goals Perform Functional verification support and assist in the design verification strategy Assist with the verification of RTL design performance goals Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power Assist with triaging, debugging and root causing functional and performance validation of the design on emulation and,or FPGA systems Minimum Qualifications
15+ years of experience in coherent cache subsystem CPU Micro-architecture and RTL Design Hands-on experience in shared L2,L3,LLC coherent cache micro-architecture, cache controller, tag, data and valid RAM design, cache pipeline, MESI or MESI-variant coherency protocols, coherent bus architecture and design like ACE, CHI, TileLink Must have gone through a complete development cycle for high performance CPU for twice or more times Experience in design with multiple power domains and clock domain crossings Experience with FinFET SRAMs and their behavioral models High quality micro-architecture documentation and communication skills Proficiency in System Verilog, Verilog and,or VHDL Experience with simulators and waveform debugging and RTL bug fixes Knowledge of logic design principles along with timing, latency, bandwidth and power implications B.S. or higher in Computer Science, Electrical Engineering, or related field Preferred Qualifications
Experience with designing RISC-V, ARM, and,or MIPS CPU Experience with Hardware multi-threading, virtualization, and SIMD designs Experience with real-time microcontroller designs Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Understanding of low-power microarchitecture techniques Understanding of RAS (Reliability, Availability and Serviceability) concepts Experience with Git and experience managing automated Jira flows triggered by source control activity Experience using Python, Perl scripting Understanding of CPU integration at SoC level Understanding of Safety and Security microarchitecture Experience with technical interaction with external vendors and,or customers What You`ll Get
A seat at the table in a small, high-impact team Opportunity to build high performance, power-efficient cache subsystem micro-architecture Competitive salary + stock grants Flexible hours A dynamic work environment that values speed, autonomy, and engineering excellence
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We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here. About the Role
We are seeking for an experienced CPU Cache Sub-system Micro architect. Responsible for delivery of micro-architecture specifications of cutting-edge high performance, highly scalable multi-core, multi-thread, power-efficient CPU Cache sub-system. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area. Key Responsibilities
Define, own, and deliver detailed micro-architecture specifications for coherent cache sub-system Implement Product and Architecture requirements Define and analyze performance modeling studies for cache subsystem design choices Feasibility studies for Micro-architecture to RTL implementation Hands-on RTL design for critical functional blocks Hands-on experience with synthesis tools for micro-architecture trade-off analysis As part of highly configurable CPU IP, configure Features Development, assessment, and refinement of parameterizable RTL design to target power, performance, area, and timing goals Perform Functional verification support and assist in the design verification strategy Assist with the verification of RTL design performance goals Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power Assist with triaging, debugging and root causing functional and performance validation of the design on emulation and,or FPGA systems Minimum Qualifications
15+ years of experience in coherent cache subsystem CPU Micro-architecture and RTL Design Hands-on experience in shared L2,L3,LLC coherent cache micro-architecture, cache controller, tag, data and valid RAM design, cache pipeline, MESI or MESI-variant coherency protocols, coherent bus architecture and design like ACE, CHI, TileLink Must have gone through a complete development cycle for high performance CPU for twice or more times Experience in design with multiple power domains and clock domain crossings Experience with FinFET SRAMs and their behavioral models High quality micro-architecture documentation and communication skills Proficiency in System Verilog, Verilog and,or VHDL Experience with simulators and waveform debugging and RTL bug fixes Knowledge of logic design principles along with timing, latency, bandwidth and power implications B.S. or higher in Computer Science, Electrical Engineering, or related field Preferred Qualifications
Experience with designing RISC-V, ARM, and,or MIPS CPU Experience with Hardware multi-threading, virtualization, and SIMD designs Experience with real-time microcontroller designs Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Understanding of low-power microarchitecture techniques Understanding of RAS (Reliability, Availability and Serviceability) concepts Experience with Git and experience managing automated Jira flows triggered by source control activity Experience using Python, Perl scripting Understanding of CPU integration at SoC level Understanding of Safety and Security microarchitecture Experience with technical interaction with external vendors and,or customers What You`ll Get
A seat at the table in a small, high-impact team Opportunity to build high performance, power-efficient cache subsystem micro-architecture Competitive salary + stock grants Flexible hours A dynamic work environment that values speed, autonomy, and engineering excellence
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