Astera Labs
Senior Electrical Validation Engineer
Astera Labs, San Jose, California, United States, 95199
Senior Electrical Validation Engineer – Astera Labs
Astera Labs (NASDAQ: ALAB) delivers rack‑scale AI infrastructure through purpose‑built connectivity solutions grounded in open standards. Our Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end‑to‑end scale‑up and scale‑out connectivity.
Base pay range:
$130,000 – $180,000 per year.
Additional compensation:
Annual bonus and RSUs.
Mission The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.
Responsibilities
Formulate a comprehensive post‑Silicon validation plan that covers ICs and board products.
Automate the testing of ICs and board products using scripting and test harnesses.
Design experiments to root‑cause unexpected behavior and identify root causes.
Report results and specification compliance to stakeholders.
Work closely with key internal customers to quantify margins and ensure robustness.
Basic Qualifications
Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
At least 2 years of experience supporting or developing complex SoC/silicon products for Server, Storage, or Networking applications.
Professional attitude with the ability to prioritize a dynamic task list, plan meetings, and work with minimal guidance.
Entrepreneurial, open‑minded behavior with a can‑do attitude and a customer‑first mindset.
Proven track record of solving problems independently and preferably as a technical lead.
Experience debugging and bring‑up of complicated SoCs with high‑speed interfaces such as PCIe/802.3 Ethernet.
Strong problem‑solving skills and ability to work independently.
Basic knowledge of high‑speed design blocks (PLL, CTLE, DFE, Tx EQ, PAM4).
Strong Python scripting and coding ability; knowledge of object‑oriented programming and Git workflow.
Proficiency using high‑speed lab equipment such as BERT, oscilloscope, and VNA.
Preferred Experience
Experience in system testing, characterization, margin analysis, and optimization of high‑speed, multi‑gigabit data links over long and short channels.
Familiarity with PCIe or Ethernet, especially electrical compliance sections.
Hands‑on experience with signal integrity testing (PCIe/Ethernet, CEM/NVMe).
Working knowledge of C or C++ for embedded firmware.
Familiarity with IEEE 802.3x Ethernet standards and NRZ/PAM‑4 signaling.
Experience with serial data specifications such as I2C and SPI.
Knowledge of schematic capture and PCB layout tools (Cadence, Altium).
Experience with simulation tools (MATLAB, Keysight ADS, PLTS).
Benefits
Medical, vision, and dental insurance.
401(k) retirement plan.
Paid paternity and maternity leave.
Flexible work arrangements.
Location San Jose, CA.
We actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+, veterans, parents, and individuals with disabilities. Astera Labs is an equal‑employment‑opportunity employer.
#J-18808-Ljbffr
Base pay range:
$130,000 – $180,000 per year.
Additional compensation:
Annual bonus and RSUs.
Mission The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar.
Responsibilities
Formulate a comprehensive post‑Silicon validation plan that covers ICs and board products.
Automate the testing of ICs and board products using scripting and test harnesses.
Design experiments to root‑cause unexpected behavior and identify root causes.
Report results and specification compliance to stakeholders.
Work closely with key internal customers to quantify margins and ensure robustness.
Basic Qualifications
Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
At least 2 years of experience supporting or developing complex SoC/silicon products for Server, Storage, or Networking applications.
Professional attitude with the ability to prioritize a dynamic task list, plan meetings, and work with minimal guidance.
Entrepreneurial, open‑minded behavior with a can‑do attitude and a customer‑first mindset.
Proven track record of solving problems independently and preferably as a technical lead.
Experience debugging and bring‑up of complicated SoCs with high‑speed interfaces such as PCIe/802.3 Ethernet.
Strong problem‑solving skills and ability to work independently.
Basic knowledge of high‑speed design blocks (PLL, CTLE, DFE, Tx EQ, PAM4).
Strong Python scripting and coding ability; knowledge of object‑oriented programming and Git workflow.
Proficiency using high‑speed lab equipment such as BERT, oscilloscope, and VNA.
Preferred Experience
Experience in system testing, characterization, margin analysis, and optimization of high‑speed, multi‑gigabit data links over long and short channels.
Familiarity with PCIe or Ethernet, especially electrical compliance sections.
Hands‑on experience with signal integrity testing (PCIe/Ethernet, CEM/NVMe).
Working knowledge of C or C++ for embedded firmware.
Familiarity with IEEE 802.3x Ethernet standards and NRZ/PAM‑4 signaling.
Experience with serial data specifications such as I2C and SPI.
Knowledge of schematic capture and PCB layout tools (Cadence, Altium).
Experience with simulation tools (MATLAB, Keysight ADS, PLTS).
Benefits
Medical, vision, and dental insurance.
401(k) retirement plan.
Paid paternity and maternity leave.
Flexible work arrangements.
Location San Jose, CA.
We actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+, veterans, parents, and individuals with disabilities. Astera Labs is an equal‑employment‑opportunity employer.
#J-18808-Ljbffr