Microchip Technology Inc.
Senior Technical Staff Engineer - Architect (DFT Lead)
Microchip Technology Inc., San Jose, California, United States, 95199
Senior Technical Staff Engineer - Architect (DFT Lead)
Microchip Technology Inc. is seeking a Senior Technical Staff Engineer - Architect (DFT Lead) based in San Jose, CA. The DFT lead works with teams across the FPGA business unit to implement testability features into the combined FPGA and ASIC SOC, from initial investigation and feasibility to tape-out, silicon validation, and characterization of test methods on Automatic Test Equipment (ATE).
Responsibilities
Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost, and DFT integration requirements are met at the block and full chip level. Define, implement, and validate DFT features at the FPGA full chip and sub-systems level.
Collaborate with cross-functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test, and quantifying full chip test coverage.
Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.
Stay current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.
Work with Test and Product engineers to support development of firmware-targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.
Communicate project status and progress to chip lead and engineering management.
Qualifications
Bachelors or Masters in engineering field
15+ years of DFT engineering experience through DFT pre- and post-silicon cycles
Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes
Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test
Familiar with DFT verification, silicon debug, memory and scan diagnostics
Experience in PHY, high-speed IO, digital communication and functional test development
Good understanding of Verilog, synthesis, physical implementation and STA
Good understanding of verification methodology
Preferred Skills And Experience
Knowledge of FPGA design flow
Knowledge of embedded design and firmware methodology
Understanding Arm or RISC IPs, high-speed interfaces such as PAM4 SerDes, DDR4/5, etc.
Experience in leading multiple FPGA/SoC projects
Travel Time 0% - 25%
Physical Attributes Feeling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others
Physical Requirements 15% walking, 15% standing, 70% sitting, 100% indoors; Usual business hours
Pay Range We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition, benefits begin day one and include retirement savings plans and an industry-leading ESPP program with a 2-year look-back feature. The annual base salary range for this position, which could be performed in California, is $90,000 - $232,000.
Range is dependent on numerous factors including job location, skills and experience.
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
Referrals increase your chances of interviewing at Microchip Technology Inc. by 2x
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Responsibilities
Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost, and DFT integration requirements are met at the block and full chip level. Define, implement, and validate DFT features at the FPGA full chip and sub-systems level.
Collaborate with cross-functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test, and quantifying full chip test coverage.
Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.
Stay current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.
Work with Test and Product engineers to support development of firmware-targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.
Communicate project status and progress to chip lead and engineering management.
Qualifications
Bachelors or Masters in engineering field
15+ years of DFT engineering experience through DFT pre- and post-silicon cycles
Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes
Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test
Familiar with DFT verification, silicon debug, memory and scan diagnostics
Experience in PHY, high-speed IO, digital communication and functional test development
Good understanding of Verilog, synthesis, physical implementation and STA
Good understanding of verification methodology
Preferred Skills And Experience
Knowledge of FPGA design flow
Knowledge of embedded design and firmware methodology
Understanding Arm or RISC IPs, high-speed interfaces such as PAM4 SerDes, DDR4/5, etc.
Experience in leading multiple FPGA/SoC projects
Travel Time 0% - 25%
Physical Attributes Feeling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others
Physical Requirements 15% walking, 15% standing, 70% sitting, 100% indoors; Usual business hours
Pay Range We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition, benefits begin day one and include retirement savings plans and an industry-leading ESPP program with a 2-year look-back feature. The annual base salary range for this position, which could be performed in California, is $90,000 - $232,000.
Range is dependent on numerous factors including job location, skills and experience.
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
Referrals increase your chances of interviewing at Microchip Technology Inc. by 2x
#J-18808-Ljbffr