Mixed Signal Model Verification Engineer

Title:

Mixed Signal Model Verification Engineer

Location:

San Jose, CA (Hybrid)

Duration:

12+ months

Must have skills

Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling

Strong understanding of HDL/SPICE co-simulations

Strong understanding of custom circuit schematic

Strong background in analog integrated circuit design

Proficiency in RTL design languages like SystemVerilog

Experience with formal equivalence checking tools like ESP

Job Description

We are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number.

It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic.

It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior.

Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.

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