Trilyon, Inc.
Mixed Signal Model Verification Engineer
Location: San Jose, CA (Hybrid)
Duration: 04 months contract
Must Have Skills
Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling
Strong understanding of HDL/SPICE co-simulations
Strong understanding of custom circuit schematic
Strong background in analog integrated circuit design
Proficiency in RTL design languages like SystemVerilog
Experience with formal equivalence checking tools like ESP
Responsibilities We are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number.
It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic. It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior.
Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.
Contact: (408) 502 9494 | (877) 874-5966 X 116
Website: www.trilyonservices.com
EEO: Trilyon is an Equal Opportunity Employer, committed to fairness and respect for all individuals. We value diversity in age, disability, ethnicity, gender, gender identity, religion, and sexual orientation, believing it drives innovation and better service. Employment decisions are made impartially, without regard to any protected characteristic under federal, state, or local law.
#J-18808-Ljbffr
Duration: 04 months contract
Must Have Skills
Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling
Strong understanding of HDL/SPICE co-simulations
Strong understanding of custom circuit schematic
Strong background in analog integrated circuit design
Proficiency in RTL design languages like SystemVerilog
Experience with formal equivalence checking tools like ESP
Responsibilities We are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number.
It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic. It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior.
Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.
Contact: (408) 502 9494 | (877) 874-5966 X 116
Website: www.trilyonservices.com
EEO: Trilyon is an Equal Opportunity Employer, committed to fairness and respect for all individuals. We value diversity in age, disability, ethnicity, gender, gender identity, religion, and sexual orientation, believing it drives innovation and better service. Employment decisions are made impartially, without regard to any protected characteristic under federal, state, or local law.
#J-18808-Ljbffr