Motion Recruitment
Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASIC
Motion Recruitment, Irvine, California, United States, 92713
Our client is a global infrastructure technology leader built on more than 60 years of innovation within the semiconductor and manufacturing space for communications.
They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team.
Responsibilities include:
Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulations Define and document chip requirements, architecture, verification and lab test plan Lab testing and debug of ASICs Documentation/application note development and customer support Requirements:
Master's and 3+ years of related experience; or PhD in Digital Signal Processing Knowledge in Communication Theory & Digital Signal Processing algorithms Experience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithms Experience in C/C++, MATLAB/Simulink Experience architecting communications systems for high performance ASIC based products is highly desirable Good hands-on skills in the lab Good oral and written communication skills Experience in Wireline Algorithms Experience in Ethernet 802.3 PHY Transceivers The Offer:
140-180K Full medical, dental, vision 401K PTO Bonus potential Motion Recruitment Partners
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Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulations Define and document chip requirements, architecture, verification and lab test plan Lab testing and debug of ASICs Documentation/application note development and customer support Requirements:
Master's and 3+ years of related experience; or PhD in Digital Signal Processing Knowledge in Communication Theory & Digital Signal Processing algorithms Experience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithms Experience in C/C++, MATLAB/Simulink Experience architecting communications systems for high performance ASIC based products is highly desirable Good hands-on skills in the lab Good oral and written communication skills Experience in Wireline Algorithms Experience in Ethernet 802.3 PHY Transceivers The Offer:
140-180K Full medical, dental, vision 401K PTO Bonus potential Motion Recruitment Partners
#J-18808-Ljbffr