SPACE EXPLORATION TECHNOLOGIES CORP
Physical Design Engineer II (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Irvine, California, United States, 92713
Overview
Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
Responsibilities
Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development
Preferred Skills and Experience
Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Understanding of CMOS digital design principles, standard cells their functionality, standard cell libraries Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic Familiar with CMOS analog circuit and physical design Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
Additional Requirements
Must be willing to work extended hours and weekends as needed
Compensation and Benefits
Pay range: Physical Design Engineer/Level II: $140,000.00 - $170,000.00 per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on job-related knowledge and skills, education, and experience. Base salary is part of SpaceX’s total rewards package, which may include long-term incentives (stock/stock options or long-term cash awards), discretionary bonuses, and opportunities to purchase additional stock via the Employee Stock Purchase Plan. Benefits include comprehensive medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, and various discounts and perks. Vacation and holidays are provided; sick leave is available for eligible employees.
Equal Opportunity and Compliance
SpaceX is an Equal Opportunity Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. To conform to ITAR, applicants may be required to be a U.S. citizen, lawful permanent resident, protected individual, or eligible to obtain required authorizations. Learn more about ITAR here.
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Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
Responsibilities
Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development
Preferred Skills and Experience
Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Understanding of CMOS digital design principles, standard cells their functionality, standard cell libraries Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic Familiar with CMOS analog circuit and physical design Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
Additional Requirements
Must be willing to work extended hours and weekends as needed
Compensation and Benefits
Pay range: Physical Design Engineer/Level II: $140,000.00 - $170,000.00 per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on job-related knowledge and skills, education, and experience. Base salary is part of SpaceX’s total rewards package, which may include long-term incentives (stock/stock options or long-term cash awards), discretionary bonuses, and opportunities to purchase additional stock via the Employee Stock Purchase Plan. Benefits include comprehensive medical, vision, and dental coverage, a 401(k) plan, disability and life insurance, paid parental leave, and various discounts and perks. Vacation and holidays are provided; sick leave is available for eligible employees.
Equal Opportunity and Compliance
SpaceX is an Equal Opportunity Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, or any other legally protected status. To conform to ITAR, applicants may be required to be a U.S. citizen, lawful permanent resident, protected individual, or eligible to obtain required authorizations. Learn more about ITAR here.
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