Intel Corporation
Senior Foundry Applications Engineer (Analog Design)
Intel Corporation, Phoenix, Arizona, United States, 85003
Senior Foundry Applications Engineer (Analog Design)
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Senior Foundry Applications Engineer (Analog Design)
role at
Intel Corporation
Intel Foundry Services is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Using this model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments.
Responsibilities
Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on AMS design and layout issue resolution.
Create content, application notes and deliver technical training/presentations.
Drive quality of design kits, documentation, and assist in tearing down barriers to successful customer design tape‑outs.
Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape‑outs, and to increase customer satisfaction.
Preferred Skills
Self‑driven and results‑oriented, capable of effectively working multiple tasks.
Analytical problem‑solving skills.
Effective communication skills, as well as experience in collaboration, listening and providing feedback.
Minimum Qualifications
US Citizenship required.
Ability to obtain a US Government Security Clearance.
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study.
5+ years of experience with advanced CMOS processes (16nm and below).
4+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting.
Hands‑on experience in one or more areas of Design Implementation and methodology especially in Custom/Analog Mixed Signal design/layout.
Preferred Qualifications
Active US Government Security Clearance with a minimum of Secret level.
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study.
Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
Hands‑on experience with analog tools and flows: Schematic entry, analog/RF simulation, extraction, post‑layout simulation, reliability validation.
Hands‑on experience with custom layout of analog blocks and Layout migration between different advanced FINFET tech nodes.
Experience in design of RF/analog/mixed‑signal blocks: Low‑noise amplifiers, filters, mixers, VCO, PLL, clock recovery, clock distribution, ADC/DAC, etc.
Customer facing experience.
Experience in SOTA Process technology (7nm and below) and PDK based technology evaluation.
Job Type Experienced Hire
Shift Shift 1 (United States of America)
Primary Location US, Arizona, Phoenix
Additional Locations US, California, Santa Clara; US, Oregon, Hillsboro
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003.
Annual Salary Range for US positions $139,710.00 – $262,680.00 USD
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Senior Foundry Applications Engineer (Analog Design)
role at
Intel Corporation
Intel Foundry Services is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Using this model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments.
Responsibilities
Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on AMS design and layout issue resolution.
Create content, application notes and deliver technical training/presentations.
Drive quality of design kits, documentation, and assist in tearing down barriers to successful customer design tape‑outs.
Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape‑outs, and to increase customer satisfaction.
Preferred Skills
Self‑driven and results‑oriented, capable of effectively working multiple tasks.
Analytical problem‑solving skills.
Effective communication skills, as well as experience in collaboration, listening and providing feedback.
Minimum Qualifications
US Citizenship required.
Ability to obtain a US Government Security Clearance.
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study.
5+ years of experience with advanced CMOS processes (16nm and below).
4+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scripting.
Hands‑on experience in one or more areas of Design Implementation and methodology especially in Custom/Analog Mixed Signal design/layout.
Preferred Qualifications
Active US Government Security Clearance with a minimum of Secret level.
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field of study.
Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
Hands‑on experience with analog tools and flows: Schematic entry, analog/RF simulation, extraction, post‑layout simulation, reliability validation.
Hands‑on experience with custom layout of analog blocks and Layout migration between different advanced FINFET tech nodes.
Experience in design of RF/analog/mixed‑signal blocks: Low‑noise amplifiers, filters, mixers, VCO, PLL, clock recovery, clock distribution, ADC/DAC, etc.
Customer facing experience.
Experience in SOTA Process technology (7nm and below) and PDK based technology evaluation.
Job Type Experienced Hire
Shift Shift 1 (United States of America)
Primary Location US, Arizona, Phoenix
Additional Locations US, California, Santa Clara; US, Oregon, Hillsboro
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003.
Annual Salary Range for US positions $139,710.00 – $262,680.00 USD
#J-18808-Ljbffr